欧美成人免费电影,国产欧美一区二区三区精品酒店,精品国产a毛片,色网在线免费观看

參數資料
型號: AD9248BCPZ-40
廠商: ANALOG DEVICES INC
元件分類: ADC
英文描述: 14-Bit, 20/40/65 MSPS Dual A/ D Converter
中文描述: DUAL 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, QCC64
封裝: 9 X 9 MM, LEAD FREE, MO-220-VMMD, LFCSP-64
文件頁數: 15/23頁
文件大?。?/td> 419K
代理商: AD9248BCPZ-40
Preliminary Technical Data
AD9248
EQUIVALENT CIRCUITS
Rev. PrE | Page 15 of 23
Figure xx.
Equivalent Analog Input Circuit
Figure xx.
Equivalent Digital Output Circuit
Figure xx.
Equivalent Digital Input Circuit
THEORY OF OPERATION
The AD9248 consists of two high performance analog-to-
digital converters (ADCs) that are based on the AD9235
converter core. The dual ADC paths are independent, except for
a shared internal band gap reference source, VREF. Each of the
ADC’s paths consists of a proprietary front end sample-and-
hold amplifier (SHA) followed by a pipelined switched
capacitor ADC. The pipelined ADC is divided into three
sections, consisting of a 4-bit first stage followed by eight 1.5-
bit stages and a final 3-bit fl ash. Each stage provides sufficient
overlap to correct for fl ash errors in the preceding stages. The
quantized outputs from each stage are combined through the
digital correction logic block into a final 12-bit result. The
pipelined architecture permits the first stage to operate on a
new input sample, while the remaining stages operate on
preceding samples. Sampling occurs on the rising edge of the
respective clock.
Each stage of the pipeline, excluding the last, consists of a low
resolution fl ash ADC and a residual multiplier to drive the next
stage of the pipeline. The residual multiplier uses the fl ash
ADC output to control a switched capacitor digital-to-analog
converter (DAC) of the same resolution. The DAC output is
subtracted from the stage’s input signal and the residual is
amplified (multiplied) to drive the next pipeline stage. The
residual multiplier stage is also called a multiplying DAC
(MDAC). One bit of redundancy is used in each one of the
stages to facilitate digital correction of flash errors. The last
stage simply consists of a flash ADC.
The input stage contains a differential SHA that can be
configured as ac- or dc-coupled in differential or single-ended
modes. The output-staging block aligns the data, carries out the
error correction, and passes the data to the output buffers. The
output buffers are powered from a separate supply, allowing
adjustment of the output voltage swing.
ANALOG INPUT
The analog input to the AD9248 is a differential switched
capacitor, SHA, that has been designed for optimum
performance while processing a differential input signal. The
SHA input accepts inputs over a wide common-mode range. An
input common-mode voltage of mid supply is recommended to
maintain optimal performance.
The SHA input is a differential switched capacitor circuit. In
Figure , the clock signal alternatively switches the SHA
between sample mode and hold mode. When the SHA is
switched into sample mode, the signal source must be capable
of charging the sample capacitors and settling within one-half
of a clock cycle. A small resistor in series with each input can
help reduce the peak transient current required from the output
stage of the driving source. Also, a small shunt capacitor can be
placed across the inputs to provide dynamic charging currents.
This passive network will create a low-pass filter at the ADC’s
相關PDF資料
PDF描述
AD9248BCPZ-65 14-Bit, 20/40/65 MSPS Dual A/ D Converter
AD9248BCPZRL7-20 14-Bit, 20/40/65 MSPS Dual A/ D Converter
AD9248BCPZRL7-40 14-Bit, 20/40/65 MSPS Dual A/ D Converter
AD9248BCPZRL7-65 14-Bit, 20/40/65 MSPS Dual A/ D Converter
AD9248BST-20 14-Bit, 20/40/65 MSPS Dual A/ D Converter
相關代理商/技術參數
參數描述
AD9248BCPZ-65 功能描述:IC ADC 14BIT DUAL 65MSPS 64LFCSP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 其它有關文件:TSA1204 View All Specifications 標準包裝:1 系列:- 位數:12 采樣率(每秒):20M 數據接口:并聯 轉換器數目:2 功率耗散(最大):155mW 電壓電源:模擬和數字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應商設備封裝:48-TQFP(7x7) 包裝:Digi-Reel® 輸入數目和類型:4 個單端,單極;2 個差分,單極 產品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6
AD9248BCPZRL-20 功能描述:IC ADC 14BIT DUAL 20MSPS 64LFCSP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 標準包裝:1 系列:- 位數:14 采樣率(每秒):83k 數據接口:串行,并聯 轉換器數目:1 功率耗散(最大):95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP(0.600",15.24mm) 供應商設備封裝:28-PDIP 包裝:管件 輸入數目和類型:1 個單端,雙極
AD9248BCPZRL-40 功能描述:IC ADC 14BIT DUAL 40MSPS 64LFCSP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 標準包裝:1 系列:- 位數:14 采樣率(每秒):83k 數據接口:串行,并聯 轉換器數目:1 功率耗散(最大):95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP(0.600",15.24mm) 供應商設備封裝:28-PDIP 包裝:管件 輸入數目和類型:1 個單端,雙極
AD9248BCPZRL-65 功能描述:IC ADC 14BIT DUAL 65MSPS 64LFCSP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 標準包裝:1 系列:- 位數:14 采樣率(每秒):83k 數據接口:串行,并聯 轉換器數目:1 功率耗散(最大):95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP(0.600",15.24mm) 供應商設備封裝:28-PDIP 包裝:管件 輸入數目和類型:1 個單端,雙極
AD9248BCPZRL7-20 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 20/40/65 MSPS Dual A/ D Converter
主站蜘蛛池模板: 昌吉市| 中宁县| 蓝山县| 海安县| 阳朔县| 荔波县| 青川县| 盐津县| 萝北县| 德令哈市| 金湖县| 白水县| 岳阳市| 台东县| 田东县| 长兴县| 九寨沟县| 章丘市| 肇庆市| 平利县| 德化县| 岳池县| 涿鹿县| 高唐县| 奉节县| 乌鲁木齐市| 宣恩县| 阿图什市| 长岭县| 赞皇县| 北宁市| 府谷县| 当雄县| 安顺市| 西峡县| 旺苍县| 竹北市| 汽车| 广德县| 宁武县| 茌平县|