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參數資料
| 型號： | AD9500TQ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號調理 |
| 英文描述： | Digitally Programmable Delay Generator |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, CDIP24 |
| 封裝： | 0.300 INCH, CERDIP-24 |
| 文件頁數： | 3/11頁 |
| 文件大小： | 131K |
| 代理商： | AD9500TQ |
–25
8
C to +85
8
C
AD9500BP/BQ
Min
Typ
–55
8
C to +125
8
C
AD9500TE/TQ
Typ
Test
Level
Parameter
Temp
Max
Min
Max
Units
SUPPORT FUNCTIONS
ECL
REF
ECL
REF
Voltage Drift
14
Offset Adjust Range
IV
V
V
+25
°
C
Full
Full
–1.4
–1.3
1.1
–2
–1.2
–1.4
–1.3
1.1
–2
–1.2
V
mV/
°
C
mA
DIGITAL OUTPUTS
7
Logic “1” Voltage
Logic “0” Voltage
POWER SUPPLY
15
Positive Supply Current (+5.0 V)
VI
VI
Full
Full
–1.1
–1.1
V
V
–1.5
–1.5
I
VI
I
VI
V
+25
°
C
Full
+25
°
C
Full
+25
°
C
24
28
30
42
44
24
28
30
42
44
mA
mA
mA
mA
mW
Negative Supply Current (–5.2 V)
37
37
Nominal Power Dissipation
Power Supply Rejection Ratio
16
Full-Scale Range Sensitivity
Minimum Propagation Delay
Sensitivity
312
312
I
+25
°
C
70
300
70
300
ps/V
I
+25
°
C
150
500
150
500
ps/V
NOTES
1
Absolute maximum ratings are limiting values, to be applied individually, and beyond which serviceability of the circuit may be impaired. Functional operability under
any of these conditions is not necessarily implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
2
Typical thermal impedance
24-Lead Cerdip
θ
JA
= 56
°
C/W;
θ
JC
= 16
°
C/W
28-Leadless PLCC (Plastic)
θ
JA
= 60
°
C/W;
θ
JC
= 22
°
C/W
28-Leaded Ceramic LCC
θ
JA
= 69
°
C/W;
θ
JC
= 25
°
C/W
3
R
= 10 k
(Full-scale delay = 100 ns).
4
The digital data inputs must remain stable for the specified time prior to the LATCH ENABLE signal.
5
The digital data inputs must remain stable for the specified time after the LATCH ENABLE signal.
6
The TRIGGER and RESET inputs are differential and must be driven relative to one another. Both of these inputs are ECL compatible, but can also be used with
TTL logic families in a limited fashion.
7
Outputs terminated through 50
resistors to –2.0 V.
8
Program Delay = 0.0 ps (Digital Data = 00
). In Operation, any programmed delays are in addition to the Minimum Propagation Delay.
9
Change in total delay through AD9500, exclusive of changes in minimum propagation delay t
.
10
Measured from the 50% transition point of the reset signal input, to the 50% transition point of the resetting output.
11
Minimum time from falling edge of RESET to triggering input, to ensure a valid output event.
12
Minimum time from triggering event to rising edge of RESET, to ensure a valid output event.
13
Measured from the LATCH ENABLE input to the point when the AD9500 becomes 8-bit accurate again, after a full-scale change in the programmed delay.
14
Standard 10K and 10KH ECL families operate with a 1.1 mV/
°
C drift by design.
15
Supply voltages should remain stable within
±
5% for normal operation.
16
Measured at
±
5% of –V
S
and +V
S
.
Specifications subject to change without notice.
EXPLANATION OF TEST LEVELS
Test Level
I
– 100% production tested.
II
– 100% production tested at +25
°
C, and sample tested at
specified temperatures.
III – Periodically sample tested.
IV – Parameter is guaranteed by design and characterization
testing.
V
– Parameter is a typical value only.
VI – All devices are 100% production tested at +25
°
C. 100%
production tested at temperature extremes for extended
temperature devices; sample tested at temperature ex-
tremes for commercial/industrial devices.
ORDERING GUIDE
Temperature
Ranges
Package
Descriptions
Package
Options
Model
AD9500BP –25
°
C to +85
°
C
28-Leadless PLCC (Plastic),
Industrial Temperature
24-Lead Cerdip,
Industrial Temperature
28-Leaded LCC,
Extended Temperature
24-Lead Cerdip,
Extended Temperature
P-28A
AD9500BQ –25
°
C to +85
°
C
Q-24
AD9500TE –55
°
C to +125
°
C
E-28A
AD9500TQ –55
°
C to +125
°
C
Q-24
AD9500
–3–
REV. D
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