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參數(shù)資料
| 型號： | AD9500TQ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號調理 |
| 英文描述： | Digitally Programmable Delay Generator |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, CDIP24 |
| 封裝： | 0.300 INCH, CERDIP-24 |
| 文件頁數(shù)： | 7/11頁 |
| 文件大?。?/td> | 131K |
| 代理商： | AD9500TQ |
AD9500
–7–
REV. D
INSIDE THE AD9500
The heart of the AD9500 is the linear ramp generator. A trig-
gering event at the input of the AD9500 initiates the ramp cycle.
As the ramp voltage falls, it will eventually go below the thresh-
old set up by the internal DAC (digital-to-analog converter). A
comparator monitors both the linear ramp voltage and the DAC
threshold level. The output of the comparator serves as the
output for the AD9500, and the interval from the trigger until
the output switches is the total delay time of the AD9500.
The total delay through the AD9500 is made up of two compo-
nents. The first is the full-scale programmed delay, t
D
(max)
,
determined by R
SET
and C
EXT
. The second component of the
total delay is the minimum propagation delay through the
AD9500 (t
PD
). The full-scale delay is variable from 2.5 ns to
greater than 1 ms. The internal DAC is capable of generating
256 separate programmed delays within the full-scale range (this
gives 10 ps increments for a 2.5 ns full-scale setting).
The actual programmed delay is directly related to both the
digital control data (digital data to the internal DAC) and the
RC time constant established by R
SET
and C
EXT
. The specific
relationship is as follows:
Total Delay = Minimum Propagation Delay +
Programmed Delay
= t
PD
+ (digital value/256) R
SET
(C
EXT
+ 10 pF)
Figure 3. Typical Programmed Delay Ranges
The internal DAC determines the programmed delay by way of
the threshold level at its output. The LATCH ENABLE control
for the onboard latch is active (latches) logic “HIGH.” In the
logic “LOW” state, the latch is transparent, and the internal
DAC will attempt to follow changes at the digital data inputs.
Both the LATCH ENABLE control and the data inputs are
TTL compatible. The internal DAC may be updated at any
time, but full timing accuracy may not be attained unless trig-
gering events are held off until after the DAC settling time
(t
DAC
).
Figure 4. Internal Timing Diagram
On resetting, the ramp voltage held in the timing capacitor
(C
EXT
+ 10 pF) is discharged. The AD9500 discharges the bulk
of the ramp voltage very quickly, but to maintain absolute accu-
racy, subsequent triggering events should be held off until after
the linear ramp settling time (t
LRS
). Applications which employ
high frequency triggering at a constant rate will not be affected
by the slight settling errors since they will be constant for fixed
reset-to-trigger cycles.
The RESET and TRIGGER inputs of the AD9500 are differen-
tial and must be driven relative to one another. Accordingly, the
TRIGGER and RESET inputs are ideally suited for analog or
complementary input signals. Single-ended ECL input signals
can be accommodated by using the ECL midpoint reference
(ECL
REF
) to drive one side of the differential inputs.
The output of the AD9500 consists of both Q and
Q
driver
stages, as well as the
Q
output which is used primarily for
extending the output pulsewidth. In the most direct reset con-
figuration, either the Q or the
Q
output is tied to the respective
RESET input. This generates a delayed output pulse with a
duration equal to the reset delay time (t
RD
) of approximately
6 ns. Note that the reset delay time (t
RD
) becomes extended for
very small programmed delay settings. The duration of the
output pulse can be extended by driving the reset inputs with the
Q
output through an RC network (see “Extended Output
Pulsewidth” application). Using the
Q
output to drive the
reset circuit avoids loading the Q or
Q
outputs.
Values in the specification table are based on 5 ns FSR test
conditions. Nearly all dynamic specifications degrade for longer
full scales. For details of performance change, request the appli-
cation note “Using Digitally Programmable Delay Generators.”
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