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參數資料
| 型號： | AD9500TQ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號調理 |
| 英文描述： | Digitally Programmable Delay Generator |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, CDIP24 |
| 封裝： | 0.300 INCH, CERDIP-24 |
| 文件頁數： | 4/11頁 |
| 文件大小： | 131K |
| 代理商： | AD9500TQ |
AD9500
–4–
REV. D
PIN FUNCTION DESCRIPTIONS
Pin Name
Description
D
4
–D
6
D
7
(MSB)
One of eight digital inputs used to set the programmed delay.
One of eight digital inputs used to set the programmed delay. D
7
(MSB) is the most significant bit of the
digital input word.
ECL midpoint reference, nominally –1.3 V. Use of the ECL
REF
allows either of the TRIGGER or RESET
inputs to be configured for single-ended ECL inputs.
The OFFSET ADJUST is used to adjust the minimum propagation delay (t
PD
), by pulling or pushing a
small current out of or into the pin.
C
S
allows the full-scale range to be extended by using an external timing capacitor. The value of C
EXT
,
connected between C
S
and +V
S
, may range from no external capacitance to 0.1
μ
F+.
See R
S
(C
INTERNAL
= 10 pF).
Positive supply terminal, nominally +5.0 V.
Noninverted input of the edge-sensitive differential trigger input stage. The output at Q will be delayed by
the programmed delay, after the triggering event. The programmed delay is set by the digital input word.
The TRIGGER input must be driven in conjunction with the
TRIGGER
input.
Inverted input of the edge-sensitive differential trigger input stage. The output at Q will be delayed by the
programmed delay, after the triggering event. The programmed delay is set by the digital input word. The
TRIGGER
input must be driven in conjunction with the TRIGGER input.
Inverted input of the level-sensitive differential reset input stage. The output at Q will be reset after a signal
is received at the reset inputs. In the “minimum configuration,” the minimum output pulsewidth will be
equal to the “reset propagation delay,” t
RD
. The RESET input must be driven in conjunction with the
RESET
input.
Noninverted input of the level-sensitive differential reset input stage. The output at Q will be reset after a
signal is received at the reset inputs. In the “minimum configuration,” the minimum output pulsewidth will
be equal to the “reset propagation delay,” t
RD
. The
RESET
input must be driven in conjunction with the
RESET input.
One of two complementary ECL outputs. A “triggering” event at the inputs will produce a logic HIGH on
the Q output. A “resetting” event at the inputs will produce a logic LOW on the Q output.
One of two complementary ECL outputs. A “triggering” event at the inputs will produce a logic LOW on
the
Q
output. A “resetting” event at the inputs will produce a logic HIGH on the
Q
output.
Q
output is parallel to the
Q
output. The
Q
output is typically used to drive delaying circuits for extend-
ing output pulsewidths. A “triggering” event at the inputs will produce a logic LOW on the
Q
R
output. A
“resetting” event at the inputs will produce a logic HIGH on the
Q
R
output.
The collector common for the ECL output stage. The collector common may be tied to +5.0 V, but nor-
mally it is tied to the circuit ground for standard ECL outputs.
Negative supply terminal, nominally –5.2 V.
R
S
is the reference current setting terminal. An external setting resistor, R
SET
, connected between R
S
and
–V
S
determines the internal reference current. See C
S
(250
≤
R
SET
≤
50 k
).
The ground return for the TTL and analog inputs.
Transparent TTL latch control line. A logic HIGH on the LATCH ENABLE freezes the digital code at the
logic inputs. A logic LOW on the LATCH ENABLE allows the internal current levels to be continuously
updated through the logic inputs D
0
thru D
7
.
One of eight digital inputs used to set the programmed delay. D
0
(LSB) is the least significant bit of the
digital input word.
One of eight digital inputs used to set the programmed delay.
ECL
REF
OFFSET ADJUST
C
S
+V
S
TRIGGER
TRIGGER
RESET
RESET
Q
Q
Q
R
ECL COMMON
–V
S
R
S
GROUND
LATCH ENABLE
D
0
(LSB)
D
3
–D
1
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