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參數(shù)資料
| 型號： | AD9802 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | .50" x 50 Black/Clear 240 Industrial Label Supply RoHS Compliant: NA |
| 中文描述： | CCD信號處理器電子照相機(jī) |
| 文件頁數(shù)： | 11/20頁 |
| 文件大小： | 366K |
| 代理商： | AD9802 |
AD9802
–11–
REV. 0
droop specifications needed. A capacitor value of 0.01
μ
F will
result in a droop of less than 10 LSB across one video line, and
requires only a CLAMP pulse of 1
μ
s to charge up. A larger
capacitor may be used to reduce droop, but then a longer
CLAMP pulse may be necessary.
SHA
ADCIN
CML
SHABYP
1V p-p
+3V
ADCMODE
AD9802
VRT
500
V
C
IN
CLAMP
AD8047
500
V
SD210
VRB
Figure 26. Video Clamp Circuit
1.0
0
2
1.00
600
100
200
300
400
500
0.5
2
0.5
700
800
900
1023
Figure 27. Direct ADC-Mode Typical INL
1.0
0
2
1.00
600
100
200
300
400
500
0.5
2
0.5
700
800
900
1023
Figure 28. Direct ADC-Mode Typical DNL
FREQUENCY – MHz
0
–100
0
9.0
A
Figure 29. Direct ADC Mode Typical FFT; F
IN
= 3.58 MHz,
F
S
= 18 MHz
Figures 27–29 show the typical linearity and distortion perfor-
mance of the AD9802 in direct ADC mode.
Digitally Programmable Gain Control
T he AD9802’s PGA is controlled by an analog input voltage of
0.3 V to 2.7 V. In some applications, digital gain control is
preferable. Figure 30 shows a circuit using Analog Devices’
AD8402 Digital Potentiometer to generate the PGA control
voltage. T he AD8402 functions as two individual potentiom-
eters, with a serial digital interface to program the position of
each wiper over 256 positions. T he device will operate with 3V
or 5 V supplies, and features a power-down mode and a reset
function.
T o keep external components to a minimum, the ends of the
“potentiometers” can be tied to ground and +3 V. One pot is
used for the coarse gain adjust, PGACONT 1, with steps of
about 0.2 dB/LSB. T he other pot is used for fine gain control,
PGAC ONT 2, and is capable of around 0.01 dB steps if all
eight bits are used. T he two outputs should be filtered with
1
μ
F or larger capacitors to minimize noise into the PGACONT
pins of the AD9802.
14
13
12
11
10
9
8
1
2
3
4
5
6
7
AD8402-10
+3V
+3V
SDI CLK
RS
SHDN
CS
0.1
m
F
1
m
F
+3V
PGACONT1
1
m
F
PGACONT2
Figure 30. Digital Control of PGA
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