
AD9802
–13–
REV. 0
Input Configurations
Input
J8
none
J9
J9
JP1
open
open
open
[ ... don’t care...
JP2
short
short
short
JP3
open
open
open
JP4
open
short
open
JP5
open
open
short
]
JP8
open
open
open
short
JP9
short
short
short
open
JP10
open
open
open
short
Standard CCD Input
Grounded Input T est
Buffered Input*
Direct ADC Input
(9802 only)
*When using the buffer amplifier,
±
5 V must be connected to AVCC and AVSS, and R4 should be removed.
Jumper Descriptions
JP1
Connect to bypass the input coupling capacitor C18.
JP2
Connect to short PIN and DIN (Pins 26 and 27 of the
AD9801) together.
JP3
Connects PIN to the dc level set by the wiper of R1.
JP4
Connect to short the input coupling capacitor to ground,
for test purposes.
JP5
Connects the output of the buffer amplifier to the
AD9801/AD9802 input.
JP6
Connects the AD9801/AD9802’s DRVDD pin to the
VDD supply through ferrite bead FB6.
JP7
Connects the AD9801/AD9802’s DRVDD pin to the
+3D supply.
JP8
Connects the output of the AD8047 op amp to the
direct ADC input of the AD9802. T his jumper should
never be connected on the AD9801-EB.
JP9
Selects the regular camera mode of operation on the
AD9802
.
T his jumper should always be in place on the
AD9801-EB.
JP10
Selects the direct ADC input mode on the AD9802
.
T his jumper should never be connected on the
AD9801-EB.
T est Point Descriptions
T P1
Input signal at J8.
T P2
Input signal at PIN/DIN of AD9801/AD9802.
T P3
PGACONT 1 voltage.
T P4
PGACONT 2 voltage.
T P5
ST ANDBY pin, pull high to enable power-down mode.
T P6
CLPDM at AD9801/AD9802.
T P7
SHD at AD9801/AD9802.
T P8
SHP at AD9801/AD9802.
T P9
CLPOB at AD9801/AD9802.
T P10 PBLK at AD9801/AD9802.
T P11 ADCCLK at AD9801/AD9802.
T P12 VDD
T P13 AVCC
T P14 AVSS
T P15 AGND
T P16 DGND
T P17 +3D
T P18 +3/5D
Prototype Area
T he top left hole in the prototyping area is connected to
AGND. T he bottom right hole is connected to AVCC.