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參數資料
型號: AD9821
廠商: Analog Devices, Inc.
英文描述: Complete 12-Bit 40 MSPS Imaging Signal Processor
中文描述: 完整的12位40 MSPS的影像信號處理器
文件頁數: 3/16頁
文件大?。?/td> 277K
代理商: AD9821
REV. 0
AD9821
–3–
IMAGER-MODE SPECIFICATIONS
Parameter
Min
Typ
Max
Unit
Notes
P
OWER CONSUMPTION
150
mW
See TPC 1 for Power vs. Sample Rate
MAXIMUM CLOCK RATE
40
MHz
ANALOG INPUTS (VIN+, VIN–)
Input Common-Mode Range
*
Max Input Amplitude
*
Max Optical Black Pixel Amplitude
*
0
1.0
1.8
V
V p-p
mV
Linear operating range for VIN+, VIN–
Defined as VIN+ minus VIN–
For stable Clamp at max VGA gain
±
30
VARIABLE GAIN AMPLIFIER (VGA)
Gain Control Resolution
Gain Monotonicity
Gain Range
Min Gain (VGA Gain Code 00)
Max Gain (VGA Gain Code 1023)
1024
Guaranteed
Steps
See Figure 11 for VGA Gain Curve
0
36
dB
dB
BLACK LEVEL CLAMP
Clamp Level Resolution
Clamp Level
Min Clamp Level
Max Clamp Level
256
Steps
Measured at ADC Output
0
255
LSB
LSB
SYSTEM PERFORMANCE
Gain Accuracy
Min Gain
Max Gain
Peak Nonlinearity, 500 mV Input
Total Output Noise
Power Supply Rejection (PSR)
Specifications Include Entire Signal Chain
–1
34.5
0
35.5
0.3
0.5
40
+1
36.5
dB
dB
%
LSB rms
dB
12 dB Gain Applied
AC Grounded Input, 6 dB Gain Applied
Measured with Step Change on Supply
POWER-UP RECOVERY TIME
Reference Standby Mode
Total Power-Down Mode
Power-Off Condition
Normal Clock Signals Applied
1
3
10
ms
ms
ms
*
Input Signal Characteristics defined as follows:
30mV MAX
OB PIXEL
1V p-p MAX
INPUT SIGNAL RANGE
VIN+
VIN–
GND
+1.8V
INPUT
CM RANGE
Specifications subject to change without notice.
(T
MIN
to T
MAX
, AVDD = DVDD = 3.0 V, f
DATACLK
= 40 MHz, unless otherwise noted.)
相關PDF資料
PDF描述
AD9821KST Complete 12-Bit 40 MSPS Imaging Signal Processor
AD9822 Complete 14-Bit CCD/CIS Signal Processor
AD9822JR Complete 14-Bit CCD/CIS Signal Processor
AD9822JRS Complete 14-Bit CCD/CIS Signal Processor
AD9823 Correlated Double Sampler (CDS)
相關代理商/技術參數
參數描述
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