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參數(shù)資料
| 型號： | AD9821 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Complete 12-Bit 40 MSPS Imaging Signal Processor |
| 中文描述： | 完整的12位40 MSPS的影像信號處理器 |
| 文件頁數(shù)： | 8/16頁 |
| 文件大小： | 277K |
| 代理商： | AD9821 |
REV. 0
–8–
AD9821
IMAGER MODE AND AUX MODE TIMING
DATACLK
OUTPUT
DATA
VIN+
N
N+1
N+2
N+8
N+9
N–10
N–9
N–8
N–1
N
t
OD
t
H
VIN–
NOTES:
1. VIN+ AND VIN– SIGNALS ARE SAMPLED AT DATACLK RISING EDGES (CAN BE INVERTED USING THE CONTROL REGISTER).
2. INTERNAL SAMPLING DELAY (APERTURE)
t
ID
IS TYPICALLY 3 ns.
3. OUTPUT DATA LATENCY IS NINE DATACLK CYCLES.
t
CONV
t
ID
Figure 5. Imager Mode Timing
IMAGER
SIGNAL
EFFECTIVE PIXELS
CLPOB
OPTICAL BLACK PIXELS
HORIZONTAL
BLANKING
EFFECTIVE PIXELS
PBLK
NOTES:
1. CLPOB WILL OVERWRITE PBLK. PBLK WILL NOT AFFECT CLAMP OPERATION IF OVERLAPPING CLPOB.
2. PBLK SIGNAL IS OPTIONAL.
3. DIGITAL OUTPUT DATA WILL BE ALL ZEROS DURING PBLK. OUTPUT DATA LATENCY IS NINE DATACLK CYCLES.
OUTPUT
DATA
EFFECTIVE PIXEL DATA
OB PIXEL DATA
EFFECTIVE DATA
Figure 6. Typical Imager Mode Line Clamp Timing
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9821KST | Complete 12-Bit 40 MSPS Imaging Signal Processor |
| AD9822 | Complete 14-Bit CCD/CIS Signal Processor |
| AD9822JR | Complete 14-Bit CCD/CIS Signal Processor |
| AD9822JRS | Complete 14-Bit CCD/CIS Signal Processor |
| AD9823 | Correlated Double Sampler (CDS) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9821KST | 制造商:Analog Devices 功能描述:AFE Video 1ADC 12-Bit 3.3V 48-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:12 BIT 40 MSPS IMAGING SIGNAL PROCESSOR - Bulk |
| AD9821KSTRL | 制造商:Analog Devices 功能描述:AFE Video 1ADC 12-Bit 3.3V 48-Pin LQFP T/R 制造商:Rochester Electronics LLC 功能描述:12 BIT 40 MSPS IMAGING SIGNAL PROCESSOR - Tape and Reel |
| AD9821KSTZ | 制造商:Analog Devices 功能描述:AFE Video 1ADC 12-Bit 3.3V 48-Pin LQFP |
| AD9821KSTZRL | 制造商:Analog Devices 功能描述:AFE Video 1ADC 12-Bit 3.3V 48-Pin LQFP T/R |
| AD9821KSTZRL7 | 制造商:Analog Devices 功能描述:AFE Video 1ADC 12-Bit 3.3V 48-Pin LQFP T/R 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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