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參數資料
| 型號： | AD9822 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Complete 14-Bit CCD/CIS Signal Processor |
| 中文描述： | 完整的14位防治荒漠化公約/ CIS信號處理器 |
| 文件頁數： | 11/15頁 |
| 文件大小： | 150K |
| 代理商： | AD9822 |
REV. A
AD9822
–11–
PGA Gain Registers
There are three PGA registers for individually programming the gain in the red, green, and blue channels. Bits D8, D7, and D6 in
each register must be set low, and bits D5 through D0 control the gain range in 64 increments. See Figure 13 for a graph of the PGA
Gain versus PGA register code. The coding for the PGA registers is straight binary, with an all “zeros” word corresponding to the
minimum gain setting (1x) and an all “ones” word corresponding to the maximum gain setting (5.7x).
Table IV. PGA Gain Register Settings
D8
D7
D6
D5
D4
D3
D2
D1
D0
Gain (V/V)
Gain (dB)
Set to 0
Set to 0
Set to 0
MSB
LSB
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
*
1
1.0
1.013
5.4
5.7
0.0
0.12
14.6
15.1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
*
Power-on default value.
Offset Registers
There are three PGA registers for individually programming the offset in the red, green, and blue channels. Bits D8 through D0
control the offset range from –350 mV to +350 mV in 512 increments. The coding for the offset registers is sign magnitude, with D8
as the sign bit. Table V shows the offset range as a function of the Bits D8 through D0.
Table V. Offset Register Settings
D8
D7
D6
D5
D4
D3
D2
D1
D0
Offset (mV)
MSB
LSB
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
*
1
0
+1.2
+350
0
–1.2
–350
0
1
1
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
1
1
1
1
1
1
1
1
1
*
Power-on default value.
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相關代理商/技術參數 |
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| AD9822-EB | 制造商:Analog Devices 功能描述: |
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| AD9822JRS | 制造商:Analog Devices 功能描述:AFE Video 1ADC 14-Bit 5V 28-Pin SSOP |
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