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參數資料
| 型號： | AD9822 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Complete 14-Bit CCD/CIS Signal Processor |
| 中文描述： | 完整的14位防治荒漠化公約/ CIS信號處理器 |
| 文件頁數： | 3/15頁 |
| 文件大小： | 150K |
| 代理商： | AD9822 |
–3–
REV. A
DIGITAL SPECIFICATIONS
Parameter
Symbol
Min
Typ
Max
Unit
LOGIC INPUTS
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
V
IH
V
IL
I
IH
I
IL
C
IN
2.0
V
V
μ
A
μ
A
pF
0.8
10
10
10
LOGIC OUTPUTS
High Level Output Voltage
Low Level Output Voltage
High Level Output Current
Low Level Output Current
V
OH
V
OL
I
OH
I
OL
4.5
V
V
μ
A
μ
A
0.1
50
50
Specifications subject to change without notice.
TIMING SPECIFICATIONS
Parameter
Symbol
Min
Typ
Max
Unit
CLOCK PARAMETERS
3-Channel Pixel Rate
1-Channel Pixel Rate
ADCCLK Pulsewidth
CDSCLK1 Pulsewidth
CDSCLK2 Pulsewidth
CDSCLK1 Falling to CDSCLK2 Rising
ADCCLK Falling to CDSCLK2 Rising
CDSCLK2 Rising to ADCCLK Rising
CDSCLK2 Falling to ADCCLK Falling
CDSCLK2 Falling to CDSCLK1 Rising
ADCCLK Falling to CDSCLK1 Rising
Aperture Delay for CDS Clocks
t
PRA
t
PRB
t
ADCLK
t
C1
t
C2
t
C1C2
t
ADC2
t
C2ADR
t
C2ADF
t
C2C1
t
ADC1
t
AD
67
80
30
10
10
0
0
0
30
30
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
40
40
2
SERIAL INTERFACE
Maximum SCLK Frequency
SLOAD to SCLK Setup Time
SCLK to SLOAD Hold Time
SDATA to SCLK Rising Setup Time
SCLK Rising to SDATA Hold Time
SCLK Falling to SDATA Valid
f
SCLK
t
LS
t
LH
t
DS
t
DH
t
RDV
10
10
10
10
10
10
MHz
ns
ns
ns
ns
ns
DATA OUTPUT
Output Delay
3-State to Data Valid
Output Enable High to 3-State
Latency (Pipeline Delay)
t
OD
t
DV
t
HZ
8
10
10
3 (Fixed)
ns
ns
ns
Cycles
Specifications subject to change without notice.
(T
MIN
to T
MAX
, AVDD = 5 V, DRVDD = 5 V, CDS Mode, f
ADCCLK
= 15 MHz, f
CDSCLK1
= f
CDSCLK2
= 5 MHz,
C
L
= 10 pF, unless otherwise noted.)
(T
MIN
to T
MAX
, AVDD = 5 V, DRVDD = 5 V)
NOTES
1
Linear input signal range is from 2 V to 4 V when the CCD’s reference level is clamped to 4 V by the AD9822’s input clamp.
1V TYP
RESET TRANSIENT
4V SET BY INPUT CLAMP (3V OPTION ALSO AVAILABLE)
2V p-p MAX INPUT SIGNAL RANGE
2
The PGA Gain is approximately “l(fā)inear in dB” and follows the equation:
Gain
=
+
[
.
. [
4 7
]
]
5 7
1
63
– G
63
where
G
is the register value. See Figure 13.
Specifications subject to change without notice.
AD9822
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相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9822-EB | 制造商:Analog Devices 功能描述: |
| AD9822JR | 制造商:Analog Devices 功能描述:AFE Video 1ADC 14-Bit 5V 28-Pin SOIC W |
| AD9822JRRL | 制造商:Analog Devices 功能描述:AFE Video 1ADC 14-Bit 5V 28-Pin SOIC W T/R 制造商:Rochester Electronics LLC 功能描述:14 BIT AFE WITH 12 BIT LINEARITY - Bulk |
| AD9822JRS | 制造商:Analog Devices 功能描述:AFE Video 1ADC 14-Bit 5V 28-Pin SSOP |
| AD9822JRSRL | 制造商:Analog Devices 功能描述:AFE Video 1ADC 14-Bit 5V 28-Pin SSOP T/R 制造商:Rochester Electronics LLC 功能描述:14 BIT AFE WITH 12 BIT LINEARITY - Bulk |
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