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參數資料
| 型號： | AD9824KCP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號調理 |
| 英文描述： | Complete 14-Bit 30 MSPS CCD Signal Processor |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, QCC48 |
| 封裝： | 7 X 7 MM, LFCSP-48 |
| 文件頁數： | 3/24頁 |
| 文件大?。?/td> | 438K |
| 代理商： | AD9824KCP |
REV. 0
–3–
AD9824
Parameter
Min
Typ
Max
Unit
Notes
P
OWER CONSUMPTION
153
mW
See TPC 1 for Power Curves
MAXIMUM CLOCK RATE
30
MHz
CDS
Gain
Allowable CCD Reset Transient
1
Max Input Range Before Saturation
1
Max CCD Black Pixel Amplitude
1
0
500
dB
mV
V p-p
mV
See Input Waveform in Footnote 1
PxGA
Gain at 4 dB
1.0
200
PIXEL GAIN AMPLIFIER (
PxGA
)
Max Input Range
Max Output Range
Gain Control Resolution
Gain Monotonicity
Gain Range (Two’s Complement Coding)
Min Gain (
PxGA
Gain Code 32)
Max Gain (
PxGA
Gain Code 31)
1.0
1.6
V p-p
V p-p
Steps
64
Guaranteed
See Figure 28 for
PxGA
Gain Curve
–2.5
9.5
dB
dB
VARIABLE GAIN AMPLIFIER (VGA)
Max Input Range
Max Output Range
Gain Control Resolution
Gain Monotonicity
Gain Range
Low Gain (VGA Gain Code 77)
Max Gain (VGA Gain Code 1023)
1.6
2.0
V p-p
V p-p
Steps
1024
Guaranteed
See Figure 29 for VGA Gain Curve
2
36
dB
dB
BLACK LEVEL CLAMP
Clamp Level Resolution
Clamp Level
Min Clamp Level
Max Clamp Level
256
Steps
Measured at ADC Output
0
1020
LSB
LSB
SYSTEM PERFORMANCE
Gain Accuracy
2
Low Gain (VGA Code 77)
Max Gain (VGA Code 1023)
Peak Nonlinearity, 500 mV Input Signal
Total Output Noise
Power Supply Rejection (PSR)
Specifications Include Entire Signal Chain
Gain = (0.0353
×
Code) +3.3
5.5
38.2
6
39.4
0.1
2.0
40
6.5
40.2
dB
dB
%
LSB rms
dB
12 dB Gain Applied
AC Grounded Input, 6 dB Gain Applied
Measured with Step Change on Supply
POWER-UP RECOVERY TIME
Reference Standby Mode
Total Shutdown Mode
Power-Off Condition
Normal Clock Signals Applied
1
3
15
ms
ms
ms
NOTES
1
Input signal characteristics defined as follows:
OPTI200mV MAX
500mV TYP
RESET TRANSIENT
INPUT 1V MAX
2
PxGA
gain fixed at Code 63 (3.3 dB).
Specifications subject to change without notice.
CCD-MODE SPECIFICATIONS
(T
MIN
to T
MAX
, AVDD = DVDD = 3.0 V, f
DATACLK
= f
SHP
= f
SHD
= 30 MHz, unless otherwise noted.)
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