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參數(shù)資料
型號(hào): AD9848KST
廠商: ANALOG DEVICES INC
元件分類(lèi): 消費(fèi)家電
英文描述: CCD Signal Processors with Integrated Timing Driver
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP48
封裝: PLASTIC, LQFP-48
文件頁(yè)數(shù): 22/36頁(yè)
文件大小: 347K
代理商: AD9848KST
REV. 0
AD9848/AD9849
–22–
HORIZONTAL CLAMPING AND BLANKING
The AD9848/AD9849’s horizontal clamping and blanking
pulses are fully programmable to suit a variety of applications.
As with the vertical timing generation, individual sequences are
defined for each signal, which are then organized into multiple
regions during image readout. This allows the dark pixel clamp-
ing and blanking patterns to be changed at each stage of the
readout, in order to accommodate different image transfer tim-
ing and high-speed line shifts.
Individual CLPOB, CLPDM, and PBLK Sequences
The AFE horizontal timing consists of CLPOB, CLPDM, and
PBLK, as shown in Figure 9. These three signals are indepen-
dently programmed using the registers in Table IV. SPOL is the
start polarity for the signal, and TOG1 and TOG2 are the first
and second toggle positions of the pulse. All three signals are
active low, and should be programmed accordingly. Up to four
individual sequences can be created for each signal.
Individual HBLK Sequences
The HBLK programmable timing shown in Figure 10 is similar
to CLPOB, CLPDM, PBLK. However, there is not start polar-
ity control. Only the toggle positions are used, to designate the
start and the stop positions of the blanking period. Additionally,
there is a polarity control HBLKMASK which designates the
polarity of the horizontal clock signals H1 – H4 during the blank-
ing period. Setting HBLKMASK high will set H1 = H3 = low
and H2 = H4 = high during the blanking, as shown in Figure
11. Up to four individual sequences are available for HBLK.
(3)
(2)
(1)
HD
CLPOB
CLPDM
PBLK
. . .
NOTES
PROGRAMMABLE SETTINGS:
(1) START POLARITY (CLAMP AND BLANK REGION ARE ACTIVE LOW)
(2) FIRST TOGGLE POSITION
(3) SECOND TOGGLE POSITION
. . .
CLAMP
CLAMP
Figure 9. Clamp and Preblank Pulse Placement
(2)
(1)
HD
HBLK
. . .
NOTES
PROGRAMMABLE SETTINGS:
(1) FIRST TOGGLE POSITION = START OF BLANKING
(2) SECOND TOGGLE POSITION = END OF BLANKING
. . .
BLANK
BLANK
Figure 10. Horizontal Blanking (HBLK) Pulse Placement
Table IV. CLPOB, CLPDM, PBLK Individual Sequence Parameters
Register Name
Length
Range
Description
SPOL
TOG1
TOG2
1b
12b
12b
High/Low
0–4095 Pixel Location
0–4095 Pixel Location
Starting Polarity of Clamp and Blanking Pulses for Sequences 0–3
First Toggle Position within the Line for Sequences 0–3
Second Toggle Position within the Line for Sequences 0–3
Table V. HBLK Individual Sequence Parameters
Register Name
Length
Range
Description
HBLKMASK
HBLKTOG1
HBLKTOG2
1b
12b
12b
High/Low
0–4095 Pixel Location
0–4095 Pixel Location
Masking Polarity for H1 for Sequences 0–3 (0 = H1 Low, 1 = H1 High)
First Toggle Position within the Line for Sequences 0–3
Second Toggle Position within the Line for Sequences 0–3
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參數(shù)描述
AD9848KSTRL 制造商:Analog Devices 功能描述:10 BIT 18 MSPS 3V AFE & T - Tape and Reel 制造商:Rochester Electronics LLC 功能描述:10 BIT 18 MSPS 3V AFE & T - Tape and Reel
AD9849 制造商:AD 制造商全稱:Analog Devices 功能描述:CCD Signal Processors with Integrated Timing Driver
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AD9849AKSTRL 制造商:Analog Devices 功能描述:AFE Video 1ADC 12-Bit 3V/3.3V/5V 48-Pin LQFP T/R 制造商:Analog Devices 功能描述:AFE VID 1ADC 12-BIT 3V/3V/3.3V/3.3V/3.3V/3.3V/3.3V/5V/5V 48L - Tape and Reel 制造商:Rochester Electronics LLC 功能描述:12 BIT 30 MSPS SIGNAL PROCESSOR - Tape and Reel
AD9849AKSTZ 功能描述:IC CCD SIGNAL PROC 12BIT 48LQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 接口 - 傳感器和探測(cè)器接口 系列:- 其它有關(guān)文件:Automotive Product Guide 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:74 系列:- 類(lèi)型:觸控式傳感器 輸入類(lèi)型:數(shù)字 輸出類(lèi)型:數(shù)字 接口:JTAG,串行 電流 - 電源:100µA 安裝類(lèi)型:表面貼裝 封裝/外殼:20-TSSOP(0.173",4.40mm 寬) 供應(yīng)商設(shè)備封裝:20-TSSOP 包裝:管件
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