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參數(shù)資料
| 型號(hào)： | AD9858TLPCB |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | XO, clock |
| 英文描述： | 1 GSPS Direct Digital Synthesizer |
| 中文描述： | 1 GSPS的直接數(shù)字頻率合成器 |
| 文件頁數(shù)： | 17/32頁 |
| 文件大?。?/td> | 1412K |
| 代理商： | AD9858TLPCB |
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AD9858
The frequency detection block works as follows. The
comparison logic in the frequency detection circuitry operates
one eighth of the DDS system clock. A comparison is made of
the frequencies present at the PD input and the DIV input over
19 DDS clock cycles.
Rev. A | Page 17 of 32
To ensure that frequency lock detection is achieved while the
frequency difference is within the PLL lock range, the slew rate
of the VCO input should be limited such that the lock range
cannot be traversed within 152 system clock cycles. The slew
rate of the VCO input is determined by the programmed level
of frequency detect current and the size of the zero
compensation capacitor according to the following relationship:
Z
det
f
C
I
dt
dv
=
Once frequency detection occurs, the loop is closed and the
loop is lock based on the current programmed for the wide
closed-loop mode. It is important that the loop be designed for
closed-loop stability while in the wide closed-loop mode. In this
mode, less phase margin can usually be tolerated, because this
mode is only used to enhance the lock time, but is not used in
the “l(fā)ocked” free running state. Once the wide closed-loop
mode achieves phase lock as determined by an internal lock
detector, the phase-detector/charge pump transitions into the
final closed-loop state. If no wide closed-loop current is
programmed, the loop transitions directly from the frequency
detect mode into the final closed-loop state. In the final closed-
loop state, the loop characteristics should be optimized for the
desired free running loop bandwidth.
The frequency detect mode is primarily useful in offset or
translation loop applications where the phase detector inputs
are more likely to detect large frequency transitions. For loop
applications with significant amounts of division in the feed-
back loop, the frequency detection mode may not activate. This
is due to the limited amount of frequency difference that is
experienced at the phase detector inputs. For these applications,
the primary means of accelerating the frequency settling time is
to design the loop to acquire lock with the wide closed-loop
setting and then switch to the final closed-loop setting.
As mentioned earlier, care should be taken when planning for a
large transition using the frequency detect mode to ensure that
the charge pump does not cause the VCO to overshoot the
closed-loop lock range, as cycle slipping could occur, which
would result in extended delays. Figure 30 shows two system
responses. In the first, the charge pump output current is
maximized during the frequency-detect mode so that, after
152 clock cycles, the VCO voltage has exceeded the closed-loop
lock range. The second system provides less current during the
frequency detect mode. While this results in a longer delay in
approaching the closed-loop lock range, because the system
does not exceed the closed-loop range, the fast-locking logic
shifts the charge pump into intermediary closed-loop mode,
resulting in a shorter overall frequency switching time.
TIME
V
0
Figure 30. Symbolic Representation of
Charge Pump to Loop Filter Connection
Analog Mixer
The analog mixer is included for translation loops, also known
as offset loops. The radio frequency (RF) and local oscillator
(LO) inputs are designed to operate at frequencies up to 2 GHz.
Both inputs are differential analog input stages. Both input
stages are internally dc biased and should be connected through
an external ac coupling mechanism. The expected input level is
in the range of 800 mV p-p (differential). The IF (intermediate
frequency) output is a differential analog output stage designed
to operate at frequencies less than 400 MHz. This mixer is based
on the Gilbert cell architecture.
MODES OF OPERATION
The AD9858 DDS section has three modes of operation—single
tone, frequency sweeping, and full sleep. The RF building blocks
(PFD, CP, and mixer) can be active or powered down, used or
unused, in either of the active modes.
In the single-tone mode, the device generates a single output
frequency determined by a 32-bit word (frequency tuning
word—FTW) loaded to an internal register. This frequency can
be changed as desired, and frequency hopping can be accompl-
ished at a rate limited only by the time required to update the
appropriate registers. If even faster hopping is needed, the four
profiles allow rapid hopping among the four frequencies stored
in them by means of external select pins.
The frequency-sweeping mode allows for the automation of
most of the frequency-sweeping task, making chirp and other
frequency-sweeping applications possible without the
inconvenience and possible speed limitations imposed by
multiple register operations via the I/O port.
In whichever mode the device is operating, changes in
frequency are phase continuous, which means that they do not
cause discontinuities in the phase of the output signal. The first
phase value after a frequency change is an increment of the last
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相關(guān)代理商/技術(shù)參數(shù) |
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| AD9859/PCBZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:400 MSPS, 10-Bit,1.8 V CMOS Direct Digital Synthesizer |
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