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參數資料
| 型號： | AD9858TLPCB |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | XO, clock |
| 英文描述： | 1 GSPS Direct Digital Synthesizer |
| 中文描述： | 1 GSPS的直接數字頻率合成器 |
| 文件頁數： | 27/32頁 |
| 文件大小： | 1412K |
| 代理商： | AD9858TLPCB |
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AD9858
CFR<3> is used to shut down the phase detector and charge
pump circuitry (default = 1).
Rev. A | Page 27 of 32
CFR<2> is used to shut down the DDS core and DAC and to
stop all internal clocks except SYNCLK (default = 0).
CFR<1>: SDIO Input Only
When CFR<1> = 0 (default), the SDIO pin has bidirectional
operation (2-wire serial programming mode).
When CFR<1> = 1, the serial data I/O pin (SDIO) is configured
as an input only pin (3-wire serial programming mode).
CFR<0>: LSB First
Note that this bit has an effect on device operation only if the
I/O port is configured as a serial port.
When CFR<0> = 0 (default), MSB first format is active.
When CFR<0> = 1, LSB first format is active.
Other Registers
Delta-Frequency Tuning Word (DFTW)
The DFTW register is comprised of four bytes located in
parallel addresses 0x04 to 0x07. The contents of the DFTW are
applied to the input of the frequency accumulator. Unlike the
frequency tuning word associated with the phase register
(which is a 32-bit unsigned integer), the DTFW is a 32-bit
signed integer. Because it controls the rate of change of
frequency, which can either be a positive or negative value, the
DTFW is by definition a signed number. When the device is in
the frequency-sweep mode, the output of the frequency
accumulator is added to the frequency tuning word and fed to
the phase accumulator. This provides the frequency sweep
capability of the AD9858. The DFTW controls the frequency
resolution associated with a frequency sweep.
As shown in Table 6, the most significant byte of the delta
frequency tuning word is located in parallel register address
0x07. The lesser significant bytes appear in descending order at
parallel register addresses 0x06, 0x05, and 0x04.
Delta-Frequency Ramp Rate Word (DFRRW)
The DFRRW is comprised of two bytes located in parallel
addresses 0x08 to 0x09. The DFRRW is a 16-bit unsigned
number that serves as a divider for the timer used to clock the
frequency accumulator. The timer runs at the DDS CLK rate
and generates a clock tick to the frequency accumulator. The
number stored in the DFRRW register determines the number
of DDS CLK cycles between subsequent ticks to the frequency
accumulator. Effectively, the DFRRW controls the rate at which
the DFTW is accumulated.
As shown in Table 6, the most significant byte of the DFRRW is
located in parallel register address 0x09 and the least significant
byte at address 0x08.
User Profile Registers
The user profile registers are comprised of the four frequency
tuning words and four phase adjustment words. Each pair of
frequency and phase registers forms a configurable user profile,
selected by the user profile pins.
User Profiles
The AD9858 features four user profiles (0–3), selected by profile
select pins (PS0, PS1) on the device. Each profile has its own
frequency tuning word. This allows the user to load a different
frequency tuning word into each profile, which can then be
selected as desired by the profile select pins. This makes it
possible to hop among the different frequencies at rates up to
1/8 of the SYSCLK while in the single-tone mode.
The AD9858 also provides a 14-bit phase-offset word (POW)
for each profile. The value in this register is a 14-bit unsigned
number (POW) that represents the proportional (PO/2
14
) phase
offset to be added to the instantaneous phase value. This allows
the phase of the output signal to be adjusted in fine increments
of phase (about 0.022°). It is possible to update the FTW and
POW of any profile while the AD9858 is operating at the
frequency specified by another profile and then switch to the
profile containing the newly loaded frequency. Changing the
current profile updates both parameters so care must be taken
to ensure that no unwanted parameter changes take place.
It is also possible to repeatedly write a new frequency into the
FTW register of a selected profile and to jump to the new
frequency by strobing the frequency update pin (FUD). This
allows hopping to arbitrary frequencies but is limited in the rate
at which this can be accomplished by the speed of the I/O port
(100 MHz in parallel mode) and the necessity to transfer several
bytes of data for each new frequency tuning word. This can be
accomplished rapidly enough for many applications.
Frequency Tuning Control
The output frequency of the DDS is determined by the 32-bit
frequency tuning word (FTW) and the system clock (SYSCLK).
The relationship is described in the following equation
(
)
N
O
SYSCLK
2
FTW
F
×
=
where for the AD9858
N
= 32.
In single-tone mode, the FTW is supplied by the active profile.
In frequency-sweeping mode, the FTW is the output of the
frequency accumulator.
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相關代理商/技術參數 |
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| AD9859/PCBZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:400 MSPS, 10-Bit,1.8 V CMOS Direct Digital Synthesizer |
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