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參數資料
| 型號： | AD9859YSV |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數字信號處理外設 |
| 英文描述： | 400 MSPS, 10-Bit, 1.8 V CMOS Direct Digital Synthesizer |
| 中文描述： | DSP-NUM CONTROLLED OSCILLATOR, PQFP48 |
| 封裝： | EXPOSED PAD, PLASTIC, MS-026ABC, QFP-48 |
| 文件頁數： | 15/24頁 |
| 文件大?。?/td> | 574K |
| 代理商： | AD9859YSV |
AD9859
CFR1<6>: Not Used
Rev. 0 | Page 15 of 24
CFR1<5>: DAC Power-Down Bit
CFR1<5> = 0 (default). The DAC is enabled for operation.
CFR1<5> = 1. The DAC is disabled and is in its lowest power
dissipation state.
CFR1<4>: Clock Input Power-Down Bit
CFR1<4> = 0 (default). The clock input circuitry is enabled for
operation.
CFR1<4> = 1. The clock input circuitry is disabled, and the
device is in its lowest power dissipation state.
CFR1<3>: External Power-Down Mode
CFR1<3> = 0 (default). The external power-down mode
selected is the rapid recovery power-down mode. In this mode,
when the PWRDWNCTL input pin is high, the digital logic
and the DAC digital logic are powered down. The DAC bias
circuitry, PLL, oscillator, and clock input circuitry are not
powered down.
CFR1<3> = 1. The external power-down mode selected is the
full power-down mode. In this mode, when the PWRDWNCTL
input pin is high, all functions are powered down. This includes
the DAC and PLL, which take a significant amount of time to
power up.
CFR1<2>: Not Used
CFR1<1>: SYNC_CLK Disable Bit
CFR1<1> = 0 (default). The SYNC_CLK pin is active.
CFR1<1> = 1. The SYNC_CLK pin assumes a static Logic 0
state to keep noise generated by the digital circuitry at a mini-
mum. However, the synchronization circuitry remains active
(internally) to maintain normal device timing.
CFR1<0>: Not Used, Leave at 0
Control Function Register No. 2 (CFR2)
The CFR2 is used to control the various functions, features, and
modes of the AD9859, primarily related to the analog sections
of the chip.
CFR2<23:12>: Not Used
CFR2<11>: High Speed Sync Enable Bit
CFR2<11> = 0 (default). The high speed sync enhancement is off.
CFR2<11> = 1. The high speed sync enhancement is on. This
bit should be set when attempting to use the auto-
synchronization feature for SYNC_CLK inputs beyond 50 MHz,
(200 MSPS SYSCLK). See the Synchronizing Multiple AD9859s
section for details.
CFR2<10>: Hardware Manual Sync Enable Bit
CFR2<10> = 0 (default). The hardware manual sync function is off.
CFR2<10> = 1. The hardware manual sync function is enabled.
While this bit is set, a rising edge on the SYNC_IN pin causes
the device to advance the SYNC_CLK rising edge by one
REFCLK cycle. Unlike the software manual sync enable bit, this
bit does not self-clear. Once the hardware manual sync mode is
enabled, it stays enabled until this bit is cleared. See the
Synchronizing Multiple AD9859s section for details.
CFR2<9>: CRYSTAL OUT Enable Bit
CFR2<9> = 0 (default). The CRYSTAL OUT pin is inactive.
CFR2<9> = 1. The CRYSTAL OUT pin is active. When active,
the crystal oscillator circuitry output drives the CRYSTAL OUT
pin, which can be connected to other devices to produce a refer-
ence frequency. The oscillator responds to crystals in the range
of 20 MHz to 30 MHz.
CFR2<8>: Not Used
CFR2<7:3>: Reference Clock Multiplier Control Bits
This 5-bit word controls the multiplier value out of the clock-
multiplier (PLL) block. Valid values are decimal 4 to 20 (0x04 to
0x14). Values entered outside this range bypass the clock multi-
plier. See the Phase-Locked Loop (PLL) section for details.
CFR2<2>: VCO Range Control Bit
This bit is used to control the range setting on the VCO.
When CFR2<2> == 0 (default), the VCO operates in a range of
100 MHz to 250 MHz. When CFR2<2> == 1, the VCO operates
in a range of 250 MHz to 400 MHz.
CFR2<1:0>: Charge Pump Current Control Bits
These bits are used to control the current setting on the charge
pump. The default setting, CFR2<1:0>, sets the charge pump
current to the default value of 75 μA. For each bit added (01, 10,
11), 25 μA of current is added to the charge pump current:
100 μA, 125 μA, and 150 μA.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9859YSV-REEL7 | 制造商:AD 制造商全稱:Analog Devices 功能描述:400 MSPS, 10-Bit, 1.8 V CMOS Direct Digital Synthesizer |
| AD9859YSVZ | 功能描述:IC DDS DAC 10BIT 400MSPS 48-TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數字合成 (DDS) 系列:- 產品變化通告:Product Discontinuance 27/Oct/2011 標準包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調節字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9859YSVZ | 制造商:Analog Devices 功能描述:IC 400 MSPS DDS 制造商:Analog Devices 功能描述:IC, 400 MSPS DDS |
| AD9859YSVZ | 制造商:Analog Devices 功能描述:DIRECT DIGITAL SYNTHESIZER |
| AD9859YSVZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:400 MSPS, 10-Bit,1.8 V CMOS Direct Digital Synthesizer |
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