- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373969 > AD9859YSV (ANALOG DEVICES INC) 400 MSPS, 10-Bit, 1.8 V CMOS Direct Digital Synthesizer PDF資料下載
參數(shù)資料
| 型號： | AD9859YSV |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號處理外設(shè) |
| 英文描述： | 400 MSPS, 10-Bit, 1.8 V CMOS Direct Digital Synthesizer |
| 中文描述： | DSP-NUM CONTROLLED OSCILLATOR, PQFP48 |
| 封裝： | EXPOSED PAD, PLASTIC, MS-026ABC, QFP-48 |
| 文件頁數(shù)： | 16/24頁 |
| 文件大?。?/td> | 574K |
| 代理商： | AD9859YSV |
AD9859
Other Register Descriptions
Amplitude Scale Factor (ASF)
Rev. 0 | Page 16 of 24
The ASF register stores the 2-bit auto ramp rate speed value
and the 10-bit amplitude scale factor used in the output shaped
keying (OSK) operation. In auto OSK operation, ASF <15:14>
tells the OSK block how many amplitude steps to take for each
increment or decrement. ASF<13:0> sets the maximum value
achievable by the OSK internal multiplier. In manual OSK
mode, ASF<15:14> has no effect. ASF <13:0> provide the
output scale factor directly. If the OSK enable bit is cleared,
CFR1<25> = 0, this register has no effect on device operation.
Amplitude Ramp Rate (ARR)
The ARR register stores the 8-bit amplitude ramp rate used in
the auto OSK mode. This register programs the rate at which
the amplitude scale factor counter increments or decrements. If
the OSK is set to manual mode, or if OSK enable is cleared, this
register has no effect on device operation.
Frequency Tuning Word 0 (FTW0)
The frequency tuning word is a 32-bit register that controls the
rate of accumulation in the phase accumulator of the DDS core.
Its specific role is dependent on the device mode of operation.
Phase Offset Word (POW)
The phase offset word is a 14-bit register that stores a phase
offset value. This offset value is added to the output of the phase
accumulator to offset the current phase of the output signal. The
exact value of phase offset is given by the following formula:
°
×
=
Φ
360
2
14
POW
MODES OF OPERATION
Single-Tone Mode
In single-tone mode, the DDS core uses a single tuning word.
Whatever value is stored in FTW0 is supplied to the phase
accumulator. This value can only be changed manually, which is
done by writing a new value to FTW0 and by issuing an I/O
UPDATE. Phase adjustment is possible through the phase
offset register.
PROGRAMMING AD9859 FEATURES
Phase Offset Control
A 14-bit phase offset (θ) may be added to the output of the phase
accumulator by means of the control registers. This feature provides
the user with two different methods of phase control.
The first method is a static phase adjustment, where a fixed
phase offset is loaded into the appropriate phase offset register
and left unchanged. The result is that the output signal is offset
by a constant angle relative to the nominal signal. This allows
the user to phase align the DDS output with some external
signal, if necessary.
The second method of phase control is where the user regularly
updates the phase offset register via the I/O port. By properly
modifying the phase offset as a function of time, the user can
implement a phase modulated output signal. However, both the
speed of the I/O port and the frequency of SYSCLK limit the
rate at which phase modulation can be performed.
The AD9859 allows a programmable continuous zeroing of the
phase accumulator as well as a clear and release or automatic
zeroing function. Each feature is individually controlled via the
CFR1 bits. CFR1<13> is the automatic clear phase accumulator
bit. CFR1<10> clears the phase accumulator and holds the value
to zero.
Continuous Clear Bit
The continuous clear bit is simply a static control signal that,
when active high, holds the phase accumulator at zero for the
entire time the bit is active. When the bit goes low, inactive, the
phase accumulator is allowed to operate.
Clear and Release Function
When set, the auto-clear phase accumulator clears and releases
the phase accumulator upon receiving an I/O UPDATE. The
automatic clearing function is repeated for every subsequent
I/O UPDATE until the appropriate auto-clear control bit is
cleared.
Shaped On-Off Keying
The shaped on-off keying function of the AD9859 allows the
user to control the ramp-up and ramp-down time of an on-off
emission from the DAC. This function is used in burst trans-
missions of digital data to reduce the adverse spectral impact of
short, abrupt bursts of data.
Auto and manual shaped on-off keying modes are supported.
The auto mode generates a linear scale factor at a rate deter-
mined by the amplitude ramp rate (ARR) register controlled by
an external pin (OSK). Manual mode allows the user to directly
control the output amplitude by writing the scale factor value
into the amplitude scale factor (ASF) register.
The shaped on-off keying function may be bypassed (disabled)
by clearing the OSK enable bit (CFR1<25> = 0).
The modes are controlled by two bits located in the most sig-
nificant byte of the control function register (CFR). CFR1<25>
is the shaped on-off keying enable bit. When CFR1<25> is set,
the output scaling function is enabled and CFR1<25> bypasses
the function. CFR1<24> is the internal shaped on-off keying
active bit. When CFR1<24> is set, internal shaped on-off keying
mode is active; CFR1<24> is cleared, external shaped on-off
keying mode is active. CFR1<24> is a Don’t Care if the shaped
on-off keying enable bit (CFR1<25>) is cleared. The power-up
condition is shaped on-off keying disabled (CFR1<25> = 0).
Figure 18 shows the block diagram of the OSK circuitry.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9859YSV-REEL7 | 400 MSPS, 10-Bit, 1.8 V CMOS Direct Digital Synthesizer |
| AD9862PCB | Mixed-Signal Front-End (MxFE⑩) Processor for Broadband Communications |
| AD9860 | Mixed-Signal Front-End (MxFE⑩) Processor for Broadband Communications |
| AD9860BST | Mixed-Signal Front-End (MxFE⑩) Processor for Broadband Communications |
| AD9860PCB | Mixed-Signal Front-End (MxFE⑩) Processor for Broadband Communications |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9859YSV-REEL7 | 制造商:AD 制造商全稱:Analog Devices 功能描述:400 MSPS, 10-Bit, 1.8 V CMOS Direct Digital Synthesizer |
| AD9859YSVZ | 功能描述:IC DDS DAC 10BIT 400MSPS 48-TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9859YSVZ | 制造商:Analog Devices 功能描述:IC 400 MSPS DDS 制造商:Analog Devices 功能描述:IC, 400 MSPS DDS |
| AD9859YSVZ | 制造商:Analog Devices 功能描述:DIRECT DIGITAL SYNTHESIZER |
| AD9859YSVZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:400 MSPS, 10-Bit,1.8 V CMOS Direct Digital Synthesizer |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。