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參數資料
| 型號： | AD9866BCPRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網絡 |
| 英文描述： | Broadband Modem Mixed Signal Front End |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, QCC64 |
| 封裝： | MO-220-VMMD, LFCSP-64 |
| 文件頁數： | 30/48頁 |
| 文件大小： | 1647K |
| 代理商： | AD9866BCPRL |
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AD9866
current sources (set to 0 mA via Reg. 0x12) to reduce the
IAMP’s current consumption.
Table 19. SPI Registers for TxDAC and IAMP
Address (Hex)
Bit
Description
0x0E
(0)
TxDAC output
0x10
(7)
Enable current mirror gain settings
(6:4) Secondary path first stage gain of 0
to 4 with = 1
(3)
Not used
(2:0) Primary path NMOS gain of 0 to 4
with = 1
0x11
(7)
Don’t care
(6:4) Secondary path second stage gain of
0 to 1.5 with = 0.25
(3)
Not used
(2:0) Secondary path third stage gain of 0
to 5 with = 1
0x12
(6:4) IOFF2, secondary path standing
current
(2:0) IOFF1, primary path standing current
Rev. 0 | Page 30 of 48
Tx PROGRAMMABLE GAIN CONTROL
TxPGA functionality is also available to set the peak output
current from the TxDAC or IAMP. The TxDAC and IAMP are
digitally programmable via the PGA[5:0] port or SPI over a
0 dB to 7.5 dB and 0 dB to 19.5 dB range, respectively, in
0.5 dB increments.
The TxPGA can be considered as two cascaded attenuators with
the TxDAC providing 7.5 dB range in 0.5 dB increments, and
the IAMP providing 12 dB range in 6 dB increments. As a result,
the IAMP’s composite 19.5 dB span is valid only if Reg. 0x10
remains at its default setting of 0x44. Modifying this register
setting corrupts the LUT and results in an invalid gain mapping.
TxDAC OUTPUT OPERATION
The differential current output of the TxDAC can be directed to
the IOUTP+ and IOUTP pins by setting Bit 0 of Reg. 0x0E.
Any load connected to these pins must be ground referenced to
provide a dc path for the current sources. Figure 63 shows the
outputs of the TxDAC driving a doubly terminated 1:1 trans-
former with its center-tap tied to ground. The peak-to-peak
voltage, V p-p,
across R
L
(and IOUT+ to IOUT) is equal to
2*I*(R
L
//R
S
). With I = 10 mA and R
L
= R
S
= 50 , V p-p is equal
to 0.5 V with 1 dBm of peak
power being delivered to R
L
and
1 dBm being dissipated in R
S
.
0
IOUTN–
IOUTN+
IOUTG–
IOUTG+
I
I
0 TO –7.5dB
0 TO –12dB
IAMP
R
R
R
SET
0.1
μ
F
R
S
1:1
R
L
TxDAC
Figure 63. TxDAC Output Directly via Center-Tap Transformer
The TxDAC is capable of delivering up to 10 dBm peak power
to a load, R
L
. To increase the peak power for a fixed standing
current, one must increase V p-p across IOUTP+ and
IOUTP by increasing one or more of the following parame-
ters: R
S
, R
L
(if possible), and/or the turns ratio, N, of transformer.
For example, the removal of R
S
and the use of a 2:1 impedance
ratio transformer in the previous example results in 10 dBm of
peak
power capabilities to the load. Note that increasing the
power output capabilities of the TxDAC reduces the distortion
performance due to the higher voltage swings seen at IOUTP+
and IOUTP. See Figure 27 through Figure 38 for performance
plots on the TxDAC’s ac performance. Optimum distortion
performance can typically be achieved by:
Limiting the peak positive V
IOUTP+
and V
IOUTP
to 0.8 V to
avoid onset of TxDAC’s output compression. (TxDAC’s
voltage compliance is around 1.2 V.)
Limiting V p-p seen at IOUTP+ and IOUTP to less than
1.6 V.
Applications demanding higher output voltage swings and
power drive capabilities can benefit from using the IAMP.
IAMP CURRENT MODE OPERATION
The IAMP can be configured for the current mode operation as
shown in Figure 64 for loads remaining relatively constant. In
this mode, the primary path mirrors should be used to deliver
the signal-dependent current to the load via a center-tapped
transformer, because it provides the best linearity performance.
Because the mirrors exhibit a high output impedance, they can
be easily back-terminated (if required).
For peak signal currents (IOUT
PK
up to 50 mA), only the
primary path mirror gain should be used for optimum
distortion performance and power efficiency. The primary
path’s gain should be set to 4, with the secondary path’s gain
stages set to 0 (Reg. 0x10 = 0x84). The TxDAC’s standing
current, I, can be set between 2.5 mA and 12.5 mA with the
IOUTP outputs left open. The IOUTN outputs should be
connected to the transformer, with the IOUTG (and IOUTP)
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相關代理商/技術參數 |
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| AD9866BCPZ | 功能描述:IC PROCESSOR FRONT END 64LFCSP RoHS:是 類別:RF/IF 和 RFID >> RF 前端 (LNA + PA) 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:250 系列:- RF 型:GPS 頻率:1575.42MHz 特點:- 封裝/外殼:48-TQFP 裸露焊盤 供應商設備封裝:48-TQFP 裸露焊盤（7x7） 包裝:托盤 |
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| AD9866CHIPS | 制造商:AD 制造商全稱:Analog Devices 功能描述:Broadband Modem Mixed Signal Front End |
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