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參數資料
| 型號： | AD9866BCPRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網絡 |
| 英文描述： | Broadband Modem Mixed Signal Front End |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, QCC64 |
| 封裝： | MO-220-VMMD, LFCSP-64 |
| 文件頁數： | 40/48頁 |
| 文件大小： | 1647K |
| 代理商： | AD9866BCPRL |
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AD9866
path power-down is meant to match the pipeline delay of the
last Tx burst sample such that power-down of the TxDAC and
IAMP does not impact its transmission. A 5-bit field in Reg.
0x03 sets the delay from 0 to 31 TXCLK clock cycles, with the
default
being 31 (0.62 μs with f
TxCLK
= 50 MSPS). The digital
interpolation filter is automatically flushed with midscale
samples prior to power-down, if the clock signal into the
TXCLK pin is present for 33 additional clock cycles after
TXEN
returns low. For an Rx burst, the rising edge of TXEN is used to
generate an internal signal (with no delay) that powers up the
Tx circuitry within 0.5 μs.
Rev. 0 | Page 40 of 48
The Rx path power-on/power-off can be controlled by either
TXEN or RXEN by setting Bit 2 of Reg. 0x03. In the default
setting, the falling edge of TXEN powers up the Rx circuitry
within 2 μs, while the rising edge of TXEN powers down the Rx
circuitry within 0.5 μs. If RXEN is selected as the control signal,
then its rising edge powers up the Rx circuitry and the falling
edge powers it down. It is possible to disable the fast power-
down of the Tx and/or Rx circuitry by setting Bit 1 and/or Bit 0
to 0.
POWER REDUCTION OPTIONS
The power consumption of the AD9866 can be significantly
reduced from its default setting by optimizing the power
consumption versus performance of the various functional
blocks in the Tx and Rx signal path. On the Tx path, minimum
power consumption is realized when the TxDAC output is used
directly and its standing current, I, is reduced to as low as 1 mA.
Although a slight degradation in THD performance results at
reduced standing currents, it often remains adequate for most
applications, because the op amp driver typically limits the
overall linearity performance of the Tx path. The load resistors
used at the TxDAC outputs (IOUTP+ and IOUTP) can be
increased to generate an adequate differential voltage that can
be further amplified via a power efficient op amp based driver
solution. Figure 78 shows how the supply current for the
TxDAC (Pin 43) is reduced from 55 mA to 14 mA as the
standing current is reduced from 12.5 mA to 1.25 mA. Further
Tx power savings can be achieved by bypassing or reducing the
interpolation factor of the digital filter as shown in Figure 79.
0
I
STANDING
(mA)
I
T
0
1
2
3
4
5
6
7
8
9
10
11
12
13
55
10
15
20
25
30
35
40
45
50
Figure 78. Reduction in TxDAC’s Supply Current vs. Standing Current
0
INPUT DATA RATE (MSPS)
I
D
20
30
40
50
60
70
80
55
60
65
15
20
25
30
35
40
45
50
2
×
INTERPOLATION
4
×
INTERPOLATION
1
×
(HALF-DUPLEX ONLY)
Figure 79. Digital Supply Current Consumption vs. Input Data Rate
(DVDD = DRVDD =3.3 V and
f
OUT
=
f
DATA
/10)
Power consumption on the Rx path can be achieved by reduc-
ing the bias levels of the various amplifiers contained within the
RxPGA and ADC. As previously noted, the RxPGA consists of
two CPGA amplifiers and one SPGA amplifier. The bias levels
of each of these amplifiers along with the ADC can be con-
trolled via Reg. 0x13 as shown in Table 24. The default setting
for 0x13 is 0x00.
Table 24. SPI Register for RxPGA and ADC Biasing
Address (Hex)
Bit
0x07
(4)
0x13
(7:5)
(4:3)
(2:0)
Description
ADC low power
CPGA bias adjust
SPGA bias adjust
ADC power bias adjust
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| AD9866 | Broadband Modem Mixed Signal Front End |
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| AD9866BCP | Broadband Modem Mixed Signal Front End |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9866BCPZ | 功能描述:IC PROCESSOR FRONT END 64LFCSP RoHS:是 類別:RF/IF 和 RFID >> RF 前端 (LNA + PA) 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:250 系列:- RF 型:GPS 頻率:1575.42MHz 特點:- 封裝/外殼:48-TQFP 裸露焊盤 供應商設備封裝:48-TQFP 裸露焊盤（7x7） 包裝:托盤 |
| AD9866BCPZRL | 功能描述:IC PROCESSOR FRONT END 64LFCSP RoHS:是 類別:RF/IF 和 RFID >> RF 前端 (LNA + PA) 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:250 系列:- RF 型:GPS 頻率:1575.42MHz 特點:- 封裝/外殼:48-TQFP 裸露焊盤 供應商設備封裝:48-TQFP 裸露焊盤（7x7） 包裝:托盤 |
| AD9866CHIPS | 制造商:AD 制造商全稱:Analog Devices 功能描述:Broadband Modem Mixed Signal Front End |
| AD9866-EB | 制造商:Analog Devices 功能描述: 制造商:Analog Devices 功能描述:12B MXFE CONVERTER FOR BROADBAND MODEMS - Bulk |
| AD9867 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Broadband Modem Mixed-Signal Front End |
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