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參數資料
| 型號： | AD9873-EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Analog Front End Converter for Set-Top Box, Cable Modem |
| 中文描述： | 模擬前端轉換器，用于機頂盒，電纜調制解調器 |
| 文件頁數： | 24/39頁 |
| 文件大小： | 935K |
| 代理商： | AD9873-EB |
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REV. 0
AD9873
–24–
Serial Interface Port Pin Description
SCLK—Serial Clock. The serial clock pin is used to synchronize
data to and from the AD9873 and to run the internal state
machines. SCLK maximum frequency is 15MHz. All data input
to the AD9873 is registered on the rising edge of SCLK. All
data is driven out of the AD9873 on the falling edge of SCLK.
CS—Chip Select. Active low input starts and gates a communi-
cation cycle. It allows more than one device to be used on the same
serial communications lines. The SDO and SDIO pins will go to
a high impedance state when this input is high. Chip select should
stay low during the entire communication cycle.
SDIO—Serial Data I/O. Data is always written into the AD9873
on this pin. However, this pin can be used as a bidirectional data
line. The configuration of this pin is controlled by Bit 7 of register
address 0h. The default is logic zero, which configures the SDIO
pin as unidirectional.
SDO—Serial Data Out. Data is read from this pin for protocols
that use separate lines for transmitting and receiving data. In the
case where the AD9873 operates in a single bidirectional I/O
mode, this pin does not output data and is set to a high imped-
ance state.
MSB/LSB Transfers
The AD9873 serial port can support both most significant bit
(MSB) first or least significant bit (LSB) first data formats. This
functionality is controlled by register address, 0h, Bit 6. The default
is MSB first. When this bit is set active high, the AD9873 serial
port is in LSB first format. That is, if the AD9873 is in LSB first
mode, the instruction byte must be written from least significant
bit to most significant bit. Multibyte data transfers in MSB format
can be completed by writing an instruction byte that includes the
register address of the most significant byte. In MSB first mode,
the serial port internal byte address generator decrements for each
byte required of the multibyte communication cycle. Multibyte
data transfers in LSB first format can be completed by writing
an instruction byte that includes the register address of the
least significant byte. In LSB first mode, the serial port internal
byte address generator increments for each byte required of
the multibyte communication cycle.
The AD9873 serial port controller address will increment from
1Fh to 00h for multibyte I/O operations if the MSB first mode is
active. The serial port controller address will decrement from
00h to 1Fh for multibyte I/O operations if the LSB first mode
is active.
Notes on Serial Port Operation
The AD9873 serial port configuration bits reside in Bits 6 and 7
of register address 00h. It is important to note that the configu-
ration changes
immediately
upon writing to the last bit of the
register. For multibyte transfers, writing to this register may
occur during the middle of a communication cycle. Care must be
taken to compensate for this new configuration for the remain-
ing bytes of the current communication cycle.
The same considerations apply to setting the reset bit in reg-
ister address 00h. All other registers are set to their default
values, but the software reset does not affect the bits in register
address 00h.
It is recommended to use only single byte transfers when chang-
ing serial port configurations or initiating a software reset.
A write to Bits 1, 2, and 3 of address 00h with the same logic levels
as for Bits 7, 6, and 5 (bit pattern: XY1001YX binary), allows the
user to reprogram a lost serial port configuration and to reset the
registers to their default values. A second write to address 00h
with
RESET
bit low and serial port configuration as specified
above (XY) reprograms the OSC IN Multiplier setting. A changed
f
SYSCLK
frequency is stable after a maximum of 200 f
MCLK
cycles
(= Wake–Up Time).
I6
(n)
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
CS
SCLK
SDIO
SDO
R/W
I5
(n)
I4
I3
I2
I1
I0
D7
n
D6
n
D2
0
D1
0
D0
0
D2
0
D1
0
D0
0
D7
n
D6
n
Figure 6a. Serial Register Interface Timing MSB-First
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
CS
SCLK
SDIO
SDO
I4
I3
I2
I1
I0
D7
n
D6
n
D2
0
D1
0
D0
0
I5
(n)
I6
(n)
R/W
D2
0
D1
0
D0
0
D7
n
D6
n
Figure 6b. Serial Register Interface Timing LSB-First
CS
SCLK
SDIO
t
DS
t
SCLK
t
PWL
t
DH
t
PWH
INSTRUCTION BIT 7
INSTRUCTION BIT 6
t
DS
Figure 7. Timing Diagram for Register Write to AD9873
DATA BIT n
DATA BIT n
–
1
CS
SCLK
SDIO
SDO
t
DV
Figure 8. Timing Diagram for Register Read from AD9873
TRANSMIT PATH (Tx)
Transmit Timing
The AD9873 provides a master clock MCLK and expects 6-bit
multiplexed Tx IQ data on each rising edge. Transmit symbols
are framed with the Tx SYNC input. Tx SYNC high indicates the
start of a transmit symbol. Four consecutive 6-bit data packages
form a symbol (I MSB, I LSB, Q MSB, and Q LSB).
Data Assembler
The input data stream is representative complex data. Two 6-bit
words form a 12-bit symbol component (two’s complement
format). Four input samples are required to produce one I/Q
data pair. The I/Q sample rate f
IQCLK
at the input to the first
half-band filter is a quarter of the input data rate f
MCLK
.
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