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參數資料
| 型號： | AD9873-EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Analog Front End Converter for Set-Top Box, Cable Modem |
| 中文描述： | 模擬前端轉換器，用于機頂盒，電纜調制解調器 |
| 文件頁數： | 29/39頁 |
| 文件大?。?/td> | 935K |
| 代理商： | AD9873-EB |
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REV. 0
AD9873
–29–
this analog filter to have a sufficiently flat gain and linear phase
response across the bandwidth of interest to avoid modulation
impairments. A relatively inexpensive fifth order elliptical low-pass
filter is sufficient to suppress the aliased components for HFC
network applications.
The AD9873 provides true and complement current outputs.
The full-scale output current is set by the RSET resistor at Pin 49.
The value of RSET for a particular IOUT is determined using
the following equation:
RSET
= 32
V
DACRSET
/
I
OUT
= ~ 39.4/
I
OUT
For example, if a full-scale output current of 20 mA is desired,
then
RSET
= (39.4/0.02)
, or approximately 2 k
. Every dou-
bling of the RSET value will halve the output current. Maximum
output current is specified as 20 mA.
The full-scale output current range of the AD9873 is 2 mA to
20 mA. Full-scale output currents outside of this range will
degrade SFDR performance. SFDR is also slightly affected by
output matching, that is, the two outputs should be terminated
equally for best SFDR performance. The output load should be
located as close as possible to the AD9873 package to minimize
stray capacitance and inductance. The load may be a simple
resistor to ground, an op amp current-to-voltage converter, or a
transformer-coupled circuit. It is best not to attempt to directly
drive highly reactive loads (such as an LC filter). Driving an LC
filter without a transformer requires that the filter be doubly
terminated for best performance, that is, the filter input and output
should both be resistively terminated with the appropriate values.
The parallel combination of the two terminations will determine
the load that the AD9873 will see for signals within the filter pass-
band. For example, a 50
terminated input/output low-pass filter
will look like a 25
load to the AD9873. The output compliance
voltage of the AD9873 is
–
0.5 V to +1.5 V. Any signal developed at
the DAC output should not exceed +1.5 V, otherwise, signal
distortion will result. Furthermore, the signal may extend below
ground as much as 0.5 V without damage or signal distortion.
The AD9873 true and complement outputs can be differentially
combined for common mode rejection using a broadband 1:1
transformer. Using a grounded center-tap results in signals at
the AD9873 DAC output pins that are symmetrical about ground.
As previously mentioned, by differentially combining the two
signals the user can provide some degree of common mode signal
rejection. A differential combiner might consist of a transformer
or an operational amplifier. The object is to combine or amplify
only the difference between two signals and to reject any common,
usually undesirable, characteristic, such as 60 Hz hum or
“
clock
feedthrough
”
that is equally present on both individual signals.
Connecting the AD9873 true and complement outputs to the
differential inputs of the gain programmable cable drivers AD8321
or AD8323 provides an optimized solution for the standard com-
pliant cable modem upstream channel. The cable driver
’
s gain
can be programmed through a direct 3-wire interface using the
AD9873
’
s profile registers.
3
LOW-PASS
FILTER
Tx
AD832x
DAC
AD9873
CA
75
VARIABLE GAIN
CABLE DRIVER
AMPLIFIER
CA_ENABLE
CA_DATA
CA_CLK
Figure 15. Cable Amplifier Connection
MSB
LSB
CA_DATA
CA_CLK
CA ENABLE
8
t
MCLK
8
t
MCLK
4
t
MCLK
4
t
MCLK
8
t
MCLK
Figure 16. Cable Amplifier Interface Timing
PROGRAMMING/WRITING THE AD8321/AD8323 CABLE
DRIVER AMPLIFIER GAIN CONTROL
Programming the gain of the AD832x-family cable driver amplifier
can be accomplished via the AD9873 cable amplifier control
interface. Four 8-bit registers within the AD9873 (one per profile)
store the gain value to be written to the serial 3-wire port. Data
transfers to the gain programmable cable driver amplifier are
initiated by four conditions. Each is described below:
1. Power-up and Hardware Reset
—
Upon initial power-up and
every hardware reset, the AD9873 clears the contents of the
gain control registers to 0, which defines the lowest gain set-
ting of the AD832x. Thus, the AD9873 writes all 0s out of
the 3-wire cable amplifier control interface.
2. Software Reset
—
Writing a one to Bit 5 of address 00h initiates a
software reset. On a software reset the AD9873 clears the
contents of the gain control registers to 0 for the lowest gain
and sets the profile select to 0. The AD9873 writes all 0s out
of the 3-wire cable amplifier control interface if the gain was
on a different setting (different from 0) before.
3. Change in Profile Selection
—
The AD9873 samples the
PROFILE[0], PROFILE[1] input pins together with the two
profile select bits and writes to the AD832x gain control regis-
ters when a change in profile and gain is determined. The data
written to the cable driver amplifier comes from the AD9873
gain control register associated with the current profile.
4. Write to AD9873 Cable Driver Amplifier Control Registers
–
The AD9873 will write gain control data associated with the
current profile to the AD832x whenever the selected AD9873
cable driver amplifier gain setting is changed.
Once a new stable gain value has been detected (48 to 64MCLK
cycles after initiation) data write starts with
CA_ENABLE
going
low. The AD9873 will always finish a write sequence to the cable
driver amplifier once it is started. The logic controlling data
transfers to the cable driver amplifier uses up to 200 MCLK
cycles and has been designed to prevent erroneous write cycles
from occurring.
相關PDF資料 |
PDF描述 |
|---|---|
| AD9873JS | Analog Front End Converter for Set-Top Box, Cable Modem |
| AD9874 | IF Digitizing Subsystem |
| AD9874BST | IF Digitizing Subsystem |
| AD9874EB | IF Digitizing Subsystem |
| AD9875BSTRL | Broadband Modem Mixed-Signal Front End |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9873JS | 制造商:Analog Devices 功能描述: |
| AD9874 | 制造商:AD 制造商全稱:Analog Devices 功能描述:IF Digitizing Subsystem |
| AD9874ABST | 功能描述:IC IF DIGIT SUBSYSTEM 48-LQFP RoHS:否 類別:RF/IF 和 RFID >> RF 其它 IC 和模塊 系列:- 標準包裝:100 系列:* |
| AD9874ABST | 制造商:Analog Devices 功能描述:IF DIGITIZING SYBSYSTEM ((NW)) 制造商:Analog Devices 功能描述:IC, IF DIGITIZING SUBSYSTEM, LQFP-48 |
| AD9874ABST | 制造商:Analog Devices 功能描述:IC IF DIG SUBSYSTEM |
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