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參數資料
| 型號： | AD9873-EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Analog Front End Converter for Set-Top Box, Cable Modem |
| 中文描述： | 模擬前端轉換器，用于機頂盒，電纜調制解調器 |
| 文件頁數： | 9/39頁 |
| 文件大小： | 935K |
| 代理商： | AD9873-EB |
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REV. 0
AD9873
–9–
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Pin Function
1, 84, 87
92, 95
2, 21, 70
3, 22, 72
4–15
AVDD
Analog Supply Voltage
10-/12-Bit ADC
Pin Driver Digital Ground
Pin Driver Digital Supply Voltage
Multiplexed Output of IF10-
and IF12-Bit ADCs
Multiplexed Output of I and
Q 8-Bit ADCs
Demultiplexer Synchronization
Output for IF and IQ ADCs
Master Clock Output
Demultiplexer
Digital Supply Voltage
Digital Ground
DRGND
DRVDD
IF11–IF0
16–19
Rx IQ 3
–Rx IQ 0
Rx SYNC
20
23
MCLK
24, 33, 38 DVDD
25, 34,
39, 40
26
DGND
Tx SYNC
Synchronization Input for
Transmitter
Multiplexed I and Q Input
Data for Transmitter (Two’s
Complement)
Profile Selection Inputs
Master Reset Input, Reset applies
for all Interfaces and Registers
Serial Interface Input Clock
Serial Interface Chip Select
Serial Interface Data I/O
Serial Interface Data Output
Digital Ground Tx Section
Digital Supply Voltage Tx
Transmit Power-Down
Control Input
DAC Bandgap requires 0.1
μ
F
Capacitor to Ground
Full-Scale DAC Current Output
Adjust with External Resistor
Analog Ground Tx Section
Transmitter DAC Output–
Transmitter DAC Output+
Analog Supply Voltage Tx
PLL Digital Ground
PLL Digital Supply Voltage
PLL Analog Supply Voltage
PLL Loop Filter Connection
PLL Analog Ground
Digital Ground Oscillator
Crystal Oscillator Inv. Output
Oscillator Clock Input
Digital Supply Oscillator
Cable Amplifier Control
Clock Output
27–32
Tx IQ 5
–Tx IQ 0
35, 36
37
PROFILE[1:0]
RESET
41
42
43
44
45
46
47
SCLK
CS
SDIO
SDO
DGND Tx
DVDD Tx
PWR DOWN
48
REFIO
49
FSADJ
50
51
52
53
54
55
56
57
58
59
60
61
62
63
AGND Tx
Tx–
Tx+
AVDD Tx
DGND PLL
DVDD PLL
AVDD PLL
PLL FILTER
AGND PLL
DGND OSC
XTAL
OSC IN
DVDD OSC
CA CLK
Pin No.
Mnemonic
Pin Function
64
CA DATA
Cable Amplifier Control Data
Output
Cable Amplifier Control Enable
Output
Supply Voltage Sigma Delta
Sigma Delta Output Stream 1
Sigma Delta Output Stream 0
Ground Sigma Delta
Programmable Reference Clock
Output Derived from MCLK
Analog Supply 8-Bit ADCs
Analog Ground 8-Bit ADCs
Bottom Reference Decoupling
IQ 8-Bit ADC’s Reference
Top Reference Decoupling
IQ 8-Bit ADC’s Reference
Inverting I Analog Input
Noninverting I Analog Input
Inverting Q Analog Input
Noninverting Q Analog Input
Analog Ground 10-/12-Bit ADC
65
CA ENABLE
66
67
68
69
71
DVDD SD
SDELTA1
SDELTA0
DGND SD
REF CLK
73
74, 77, 80 AGND IQ
75
AVDD IQ
REFB8
76
REFT8
78
79
81
82
83, 88, 91, AGND
96, 99
85
I IN–
I IN+
Q IN–
Q IN+
REFB10
Bottom Reference Decoupling
IF 10-Bit ADC’s Reference
Top Reference Decoupling
IF 10-Bit ADC’s Reference
Noninverting IF10 Analog Input
Inverting IF10 Analog Input
Bottom Reference Decoupling
IF 12-Bit ADC’s Reference
Top Reference Decoupling
IF 12-Bit ADC’s Reference
Inverting IF12 Analog Input
Noninverting IF12 Analog Input
Single-Ended Video Input
86
REFT10
89
90
93
IF10–
IF10+
REFB12
94
REFT12
97
98
100
IF12–
IF12+
VIDEO IN
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相關代理商/技術參數 |
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| AD9874ABST | 功能描述:IC IF DIGIT SUBSYSTEM 48-LQFP RoHS:否 類別:RF/IF 和 RFID >> RF 其它 IC 和模塊 系列:- 標準包裝:100 系列:* |
| AD9874ABST | 制造商:Analog Devices 功能描述:IF DIGITIZING SYBSYSTEM ((NW)) 制造商:Analog Devices 功能描述:IC, IF DIGITIZING SUBSYSTEM, LQFP-48 |
| AD9874ABST | 制造商:Analog Devices 功能描述:IC IF DIG SUBSYSTEM |
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