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參數資料
| 型號： | AD9883KST-110 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | 110 MSPS Analog Interface for Flat Panel Displays |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封裝： | PLASTIC, LQFP-80 |
| 文件頁數： | 14/24頁 |
| 文件大?。?/td> | 177K |
| 代理商： | AD9883KST-110 |
REV. 0
AD9883
–14–
Table VI. Control Register Map (Continued)
Write and
Read or
Read Only
Hex
Address
Default
Value
Register
Name
Bits
Function
0FH
R/
W
7:1
0
*******
Bit 7 – Clamp Function. Chooses between HSYNC for Clamp
signal or another external signal to be used for clamping.
(Logic 0 = HSYNC, Logic 1 = Clamp.)
Bit 6 – Clamp Polarity. Valid only with external Clamp signal.
(Logic 0 = active high, Logic 1 select active low.)
Bit 5 – Coast Select. Must be set to 0.
Bit 4 – Coast Polarity Override. (Logic 0 = Polarity determined by
chip, Logic 1 = Polarity set by Bit 3 in register 0Fh.)
Bit 3 – Coast Polarity. Changes polarity of external COAST signal.
(Logic = 0 = active high, Logic 1 = active low.)
Bit 2 – Seek Mode Override. (Logic 1 = allow low-power
mode, Logic 0 = disallow low-power mode.)
Bit 1 –
PWRDN
. Full Chip Power Down, active low. (Logic 0 =
Full Chip Power Down, Logic 1 = normal.)
Sync-on-Green Threshold – Sets the voltage level of the Sync-on-
Green slicer’s comparator.
Bit 2 – Red Clamp Select – Logic 0 selects clamp to ground. Logic
1 selects clamp to midscale, (voltage at Pin 37).
Bit 1 – Green Clamp Select – Logic 0 selects clamp to ground.
Logic 1 selects clamp to midscale, (voltage at Pin 37).
Bit 0 – Blue Clamp Select – Logic 0 selects clamp to ground.
Logic 1 selects clamp to midscale, (voltage at Pin 37).
Sync Separator Threshold – Sets how many internal 5 MHz clock
periods the sync separator will count to before toggling high or
low. This should be set to some number greater than the maxi-
mum Hsync or equalization pulsewidth.
Pre-Coast – Sets the number of Hsync periods that coast becomes
active prior to Vsync.
Post-Coast – Sets the number of Hsync periods that coast stays
active following Vsync.
Bit 7 – Hsync detect. It is set to Logic 1 if Hsync is present on the
analog interface, else it is set to Logic 0.
Bit 6 – AHS: Active Hsync. This bit indicates which analog Hsync
is being used. (Logic 0 = Hsync input pin, Logic 1 = Hsync from
sync-on-green).
Bit 5 – Input Hsync Polarity Detect. (Logic 0 = Active Low,
Logic 1 = Active High.)
Bit 4 – Vsync detect. It is set to Logic 1 if V-sync is present on the
analog interface, else it is set to Logic 0.
Bit 3 – AVS: Active Vsync. This bit indicates which analog Vsync
is being used. (Logic 0 = Vsync input pin, Logic 1 = Vsync from
sync separator).
Bit 2 – Output Vsync Polarity Detect. (Logic 0 = Active Low,
Logic 1 = Active High.)
Bit 1 – Sync-on-Green detect. It is set to Logic 1 if sync is present
on the green video input, else it is set to 0.
Bit 0 – Input Coast Polarity Detect. (Logic 0 = active low, Logic 1 =
active high.)
Reserved for future use.
Reserved for future use.
Reserved for future use.
Reserved for future use.
*
1
******
**
0
*****
***
0
****
****
1
***
*****
1
**
******
1
*
10H
R/
W
7:3
10111
***
Sync-on-Green
Threshold
*****
0
**
******
0
*
*******
0
11H
R/
W
7:0
00100000
Sync Separator
Threshold
12H
R/
W
7:0
00000000
Pre-Coast
13H
R/
W
7:0
00000000
Post-Coast
14H
RO
7:0
Sync Detect
15H
16H
17H
18H
R/
W
R/
W
RO
RO
7:0
7:0
7:0
7:0
Test Register
Test Register
Test Register
Test Register
NOTE
1
The AD9883 only updates the PLL divide ratio when the LSBs are written to (register 02h).
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