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參數(shù)資料
| 型號： | AD9883KST-110 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | 110 MSPS Analog Interface for Flat Panel Displays |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封裝： | PLASTIC, LQFP-80 |
| 文件頁數(shù)： | 17/24頁 |
| 文件大小： | 177K |
| 代理商： | AD9883KST-110 |
REV. 0
AD9883
–17–
0E
3
This bit is used under two conditions. It is used to select
the active Hsync when the override bit is set, (Bit 4). Alter-
nately, it is used to determine the active Hsync when not
overriding but both Hsyncs are detected.
Active Hsync Select
Table XIII. Active HSYNC Select Settings
Select
Result
0
1
HSYNC Input
Sync-on-Green Input
The default for this register is 0.
2
Vsync Output Invert
One bit that can invert the polarity of the Vsync output.
Table XIV shows the effect of this option.
0E
Table XIV. Vsync Output Invert Settings
Setting
Vsync Output
1
0
No Invert
Invert
The default setting for this register is 1.
1 Active Vsync Override
This bit is used to override the automatic Vsync selection.
To override, set this bit to Logic 1. When overriding, the
active interface is set via Bit 0 in this register.
0E
Table XV. Active Vsync Override Settings
Override
Result
0
1
Auto Determine the Active Vsync
Override, Bit 0 Determines the Active Vsync
The default for this register is 0.
0 Active Vsync Select
This bit is used to select the active Vsync when the over-
ride bit is set, (Bit 1).
0E
Table XVI. Active Vsync Select Settings
Select
Result
0
1
Vsync Input
Sync Separator Output
The default for this register is 0.
7 Clamp Input Signal Source
A bit that determines the source of clamp timing.
0F
Table XVII. Clamp Input Signal Source Settings
Clamp Function
Function
0
1
Internally Generated Clamp
Externally-Provided Clamp Signal
A 0 enables the clamp timing circuitry controlled by clamp
placement and clamp duration. The clamp position and
duration is counted from the leading edge of Hsync.
A 1 enables the external CLAMP input pin. The three
channels are clamped when the CLAMP signal is active.
The polarity of CLAMP is determined by the Clamp
Polarity bit (Register 0Fh, Bit 6).
The power-up default value is Clamp Function = 0.
6 Clamp Input Signal Polarity
A bit that determines the polarity of the externally pro-
vided CLAMP signal.
0F
Table XVIII. Clamp Input Signal Polarity Settings
Clamp Function
Function
1
0
Active LOW
Active HIGH
A Logic 1 means that the circuit will clamp when CLAMP is
HIGH, and it will pass the signal to the ADC when CLAMP
is LOW.
A Logic 0 means that the circuit will clamp when CLAMP
is LOW, and it will pass the signal to the ADC when
CLAMP is HIGH.
The power-up default value is Clamp Polarity = 1.
5 Coast Select
This bit must be set to 0.
4 Coast Input Polarity Override
This register is used to override the internal circuitry that
determines the polarity of the coast signal going into
the PLL.
0F
0F
Table XIX. Coast Input Polarity Override Settings
Override Bit
Result
0
1
Coast Polarity Determined by Chip
Coast Polarity Determined by User
The default for coast polarity override is 0.
3 Coast Input Polarity
A bit to indicate the polarity of the COAST signal that is
applied to the PLL COAST input.
0F
Table XX. Coast Input Polarity Settings
Coast Polarity
Function
0
1
Active LOW
Active HIGH
Active LOW means that the clock generator will ignore
Hsync inputs when COAST is LOW, and continue
operating at the same nominal frequency until COAST
goes HIGH.
Active HIGH means that the clock generator will ignore
Hsync inputs when COAST is HIGH, and continue
operating at the same nominal frequency until COAST
goes LOW.
This function needs to be used along with the COAST
polarity override bit, (Bit 4).
The power-up default value is 1.
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