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參數(shù)資料
| 型號(hào)： | AD9937KCPRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | TVPS00RF-25-35PB W/ PC CONTACT |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, QCC56 |
| 封裝： | MO-220-VLLD-2, LFCSP-56 |
| 文件頁數(shù)： | 18/44頁 |
| 文件大?。?/td> | 410K |
| 代理商： | AD9937KCPRL |
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REV. 0
–18–
AD9937
SERIAL INTERFACE TIMING
All of the internal registers of the AD9937 are accessed through
a 3-wire serial interface. The 3-wire interface consists of a clock
(SCK), serial load (SLD), and serial data (SDA).
The AD9937 has three different register types that are configured
by the 3-wire serial interface pins. As described in Table VII,
the three register types are control registers, system registers,
and mode registers.
Table VII. Serial Interface Registers
Register
Address
No. of Registers
Control Registers
0x00 to
0x12
24-Bit Register at Each
Address. See Table I.
VTP Sequence
System Registers
0x14
Fourteen 32-Bit System
Registers at Address
0x14. See Table II.
H/LM System
Registers
0x15
Ten 32-Bit System
Registers at Address
0x15. See Table III.
Shutter System
Registers
0x16
Five 32-Bit System
Registers at Address
0x16. See Table IV.
Mode_A
0x17
Twenty 32-Bit Mode_A
Registers at Address
0x17. See Table V.
Mode_B
0x18
Twenty 32-Bit Mode_B
Registers at Address
0x18. See Table VI.
Control Register Serial Interface
The control register 3-wire interface timing requirements are
shown in Figure 5. Writing to control registers requires eight bits of
address data followed by 24 bits of configuration data between
each active low period of SLD for each address. The SLD signal
must be kept high for at least one full SCK cycle between suc-
cessive writes to control registers.
System and Mode Register Serial Interface
The AD9937 provides two options for writing to system and
mode registers. The Page/Burst write option is used when all the
registers are going to be written to, whereas the Random Access
option is used when only one or a small contiguous sequence of
registers is going to be written to. As shown in Figure 6, the
protocol for writing to system and mode registers requires eight
bits for the address data, 12 bits for the start location, 12 bits
for the end location, and 32 bits for the register data.
Page/Burst Option
The AD9937 is automatically configured for Page/Burst mode if
both 12-bit STARTADDRESS and ENDADDRESS fields
equal 0. In this configuration, the AD9937 expects all registers
to be written to, therefore all register data must be clocked in
before the SLD pulse is asserted high. The SLD pulse is ignored
until all register data is clocked in. The Page/Burst option is
preferred when initially programming the system and mode
registers at startup.
Random Access Option
With the Random Access option, the 12-bit STARTADDRESS
and ENDADDRESS fields are typically used when writing to
one system or mode register or a small sequential number of
system or mode registers. In this mode, the address data selects
the system or mode register bank that is going to be accessed,
the 12-bit STARTADDRESS determines the first register to be
accessed, and the 12-bit ENDADDRESS determines the last
register to be accessed. Two examples of Random Access are
provided below (refer to Figure 6).
Example 1: Accessing Only One Register, HLM_Reg(6)
HLM_Reg_addr[A7:A0] = 0x15
STARTADDRESS[S11:S0] = 0x0006
ENDADDRESS[E11:E0] = 0x0006
Example 2: Accessing HLM_Reg(2), HLM_Reg(3), and
HLM_Reg(4) Sequentially
HLM_Reg_addr[A7:A0] = 0x15
STARTADDRESS[S11:S0] = 0x0002
ENDADDRESS[E11:E0] = 0x0004
SDA
SCK
SLD
A5
A6
D22
D21
D3
D2
D1
1. SDA BITS ARE INTERNALLY LATCHED ON THE RISING EDGES OF SCK.
2. THIS TIMING PATTERN MUST BE WRITTEN FOR EACH REGISTER WRITE WITH SLD REMAINING HIGH FOR AT
LEAST ONE FULL SCK PERIOD BEFORE ASSERTING SLD LOW AGAIN FOR THE NEXT REGISTER WRITE.
A7
A4
A3
A2
A1
A0
D23
....
....
D0
1
2
3
4
5
6
7
8
9
10
11
29
30
31
t
LH
32
t
DS
t
DH
t
LS
Figure 5. 3-Wire Serial Interface Timing for Control Registers
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