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參數(shù)資料
| 型號： | AD9937KCPRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | TVPS00RF-25-35PB W/ PC CONTACT |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, QCC56 |
| 封裝： | MO-220-VLLD-2, LFCSP-56 |
| 文件頁數(shù)： | 35/44頁 |
| 文件大小： | 410K |
| 代理商： | AD9937KCPRL |
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REV. 0
AD9937
–35–
HBLKTOG2
H1TOG12POL
132
133
134
135
234
1560
1559
0
1
2
3
H1
H2
154
156
233
H1MASKPOL
4
H1TOG34POL
131
HDLEN
HDLASTLEN
HBLKTOG1
HMASK
HBLK
HMASK
HBLK
VERTICAL HMASK
155
1
2
0
Figure 30. Example of Vertical HMASK Masking with HDLASTLEN > HDLEN with HMASTKSTART = 0 and HMASKSTOP = 1560
VERTICAL TIMING GENERATION
The AD9937 provides a very flexible solution for generating
vertical CCD timing, and can support multiple CCDs and differ-
ent system architectures. The 4-phase vertical transfer clocks
V1
–
V4 are used to shift each line of pixels into the horizontal
output register of the CCD. The AD9937 allows these outputs
to be individually programmed into different pulse patterns.
Vertical sequence control registers then organize the individual
vertical pulses into the desired CCD vertical timing arrangement.
The AD9937 can preprogram three unique sets of vertical transfer
pulses known as VTP0, VTP1, and VTP2. Each VTP set consists
of the four vertical clocks (V1A/B, V2, V3A/B, and V4), as shown
in Figure 32. Once preprogrammed, any one of the three unique
VTP sets can then be selected to be output in any one of the
five CCD regions by using the VTPPATSELx (x = 0, 1, 2, 3, 4)
registers. The VTP_Reg(1
–
9) registers listed in Table II are used
for generating the VTP pulse sets.
Figure 32 shows an example of programming one VTPx (x = 0, 1, 2)
pulse set. Once a VTP pulse set has been configured, multiple
repetitions of this set can be repeated to create an entire VTP
sequence. This is accomplished by using the VTPREPn
(n = 0, 1, 2, 3, 4) registers where n represents the five CCD regions.
An example of repeating a VTP set is shown in Figure 33.
CCD REGIONS
Up to five unique CCD regions can be preprogrammed using the
sequence change position registers as described in Table XVII.
The SCPx (x = 0, 1, 2, 3, 4) registers determine when the set-
tings in Mode_Reg(15
–
19) are active. For example, the SCP1
register activates the registers at Mode_Reg(16) for CCD region 1.
Note that SCP0 is not programmable. The SCP0 position always
starts at Line 0, as shown in Figure 31.
SCP0
(FIXED AT LINE 0)
SCP1 [7:0]
SCP4 [7:0]
SCP3 [7:0]
SCP2 [7:0]
CCD REGION 0
CCD REGION 1
CCD REGION 2
CCD REGION 3
CCD REGION 4
REGISTERS LOCATED AT MODE_REG(15)
ARE ACTIVE WHILE
OPERATING IN CCD REGION 0
REGISTERS LOCATED AT MODE_REG(16)
ARE ACTIVE WHILE
OPERATING IN CCD REGION 1
REGISTERS LOCATED AT MODE_REG(17)
ARE ACTIVE WHILE
OPERATING IN CCD REGION 2
REGISTERS LOCATED AT MODE_REG(18)
ARE ACTIVE WHILE
OPERATING IN CCD REGION 3
REGISTERS LOCATED AT MODE_REG(19)
ARE ACTIVE WHILE
OPERATING IN CCD REGION 4
Figure 31. Sequence Change Positions
Table XVII. Sequence Change Positions Registers
Length
(Bits)
Register
Type
Register Name
*
Range
Description
SCP1
SCP2
SCP3
SCP4
8
8
8
8
Mode_Reg(14)
Mode_Reg(14)
Mode_Reg(14)
Mode_Reg(14)
0
–
255 Line Positions
0
–
255 Line Positions
0
–
255 Line Positions
0
–
255 Line Positions
Sequence Change Position 1
Sequence Change Position 2
Sequence Change Position 3
Sequence Change Position 4
*
There is no SCP0 register. The SCP0 position is always fixed at Line 0.
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