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參數資料
| 型號： | AD9937KCPRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | TVPS00RF-25-35PB W/ PC CONTACT |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, QCC56 |
| 封裝： | MO-220-VLLD-2, LFCSP-56 |
| 文件頁數： | 29/44頁 |
| 文件大小： | 410K |
| 代理商： | AD9937KCPRL |
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REV. 0
AD9937
–29–
Vertical Sensor Transfer Gate Timing
The vertical transfer sensor gate (TG) pulses are used to trans-
fer the pixel charges from the light-sensitive image area into the
light-shielded vertical registers. When a mechanical shutter is
not being used, this transfer effectively ends the exposure
period during the image acquisition. From the light-shield
vertical registers, the image is then read out line by line using
the vertical transfer pulses in conjunction with the high speed
horizontal clocks.
The AD9937 provides four programmable vertical transfer gate
pulses (TG1A, TG1B, TG3A, and TG3B). Table XIII lists the
TG registers. Two unique TG pulses can be preprogrammed
using the TGTOG_x (x = 0, 1) registers. As shown in Figure 24,
these toggle registers reference the 12-bit H counter for resolu-
tion control at the pixel level. Once the toggle positions have
been programmed, the TGPATSELx (x = 0, 1) can be used to
select which of the two TG pulses will be output on the TG1A/
B and TG3A/B pins. The TG1A/B and TG3A/B outputs are
selected as a group. As a result, the TG1A and TG1B outputs
will always be the same. This also applies for the TG3A and
TG3B outputs. For example, if TGPATSEL0 = 0, TG1A and
TG1B will have the outputs provided by the TGTOG1_0 and
TGTOG2_0 registers.
The TGMASK register can be used to individually mask (disable)
any one of the TG outputs. For example, if TGMASK = 1, the
TG1A will not be output. All TG outputs can be disabled by
setting TGEN = 0.
SHUTTER TIMING CONTROL
CCD image exposure is controlled through use of the substrate
clock signal (OFD), which pulses the CCD substrate to clear
out accumulated charge. The AD9937 supports two types of
OFD shutter timing: normal shutter mode and high precision
shutter mode. The registers used for OFD programming are
described in Table XIV.
Normal Shutter Mode
Figure 24 shows the VD and OFD output for normal shutter
mode. Programming the OFD outputs is similar to program-
ming the TG pulse whereas two unique OFD pulses can be
preprogrammed using the OFDTOG_x (x = 0, 1) registers. The
OFDTOG_x registers reference the 12-bit HD counter as shown
in Figure 24. Once the toggle positions have been programmed,
the OFDPATSEL register is used to select which of the two
preprogrammed OFD pulses will be output. The OFD will pulse
once per line for as many lines set in the OFDNUM register.
High Precision Shutter Mode
High precision shuttering is controlled in the same way as nor-
mal shuttering but requires a second set of shutter registers. In
this mode, the OFD still pulses once per line, but the last OFD
in the field will have an additional OFD pulse whose location is
determined by the OFDHPTOG1 and OFDHPTOG2 registers.
An example of this is shown in Figure 25. Finer resolution of
the exposure time is possible using this mode. Leaving both
OFDHPTOG registers set to 4095 disables the high precision
shutter mode (default setting).
Table XIII. TG Registers
Length
(Bits)
Register
Type
Register Name
Range
Description
TGEN
TGTOG1_0
TGTOG2_0
TGTOG1_1
TGTOG2_1
TGACTLINE
TGPATSEL0
TGPATSEL1
TGMASK
1
12
12
12
12
7
1
1
4
Control 0x10
Shut_Reg(1)
Shut_Reg(1)
Shut_Reg(2)
Shut_Reg(2)
Mode_Reg(1)
Mode_Reg(1)
Mode_Reg(1)
Mode_Reg(1)
High/Low
0
–
4095 Pixel Location
0
–
4095 Pixel Location
0
–
4095 Pixel Location
0
–
4095 Pixel Location
0
–
127 Pixel Location
High/Low
High/Low
4 Individual Bits
TG Output Enable Control (0 = Disable, 1 = Enable)
TG0 Pulse Toggle Position 1
TG0 Pulse Toggle Position 2
TG1 Pulse Toggle Position 1
TG1 Pulse Toggle Position 2
Line in Field where TG Outputs are Active
TG1 A/B Pattern Selector (0 = TG0, 1 = TG1)
TG3 A/B Pattern Selector (0 = TG0, 1 = TG1)
TG Masking Control (0 = No Masking, 1 = Mask TG1A,
2 = Mask TG1B, 3 = Mask TG3A, 4 = Mask TG3B)
CLPOB
HD
VD
CCD REGION 1
CCD REGION 2
CCD REGION 0
Figure 23. Example with CLPOBEN1 = 0
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相關代理商/技術參數 |
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| AD9938BCBZ | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD9938BCPZ | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD9938KCP | 制造商:Analog Devices 功能描述:- Bulk |
| AD9940BCPZ | 功能描述:IC CDS TIMING DRIVE CONV 48LFCSP RoHS:是 類別:集成電路 (IC) >> 數據采集 - ADCs/DAC - 專用型 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:50 系列:- 類型:數據采集系統（DAS） 分辨率（位）:16 b 采樣率（每秒）:21.94k 數據接口:MICROWIRE?，QSPI?，串行，SPI? 電壓電源:模擬和數字 電源電壓:1.8 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:40-WFQFN 裸露焊盤 供應商設備封裝:40-TQFN-EP（6x6） 包裝:托盤 |
| AD9940BCPZRL | 功能描述:IC CDS TIMING DRIVE CONV 48LFCSP RoHS:是 類別:集成電路 (IC) >> 數據采集 - ADCs/DAC - 專用型 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:50 系列:- 類型:數據采集系統（DAS） 分辨率（位）:16 b 采樣率（每秒）:21.94k 數據接口:MICROWIRE?，QSPI?，串行，SPI? 電壓電源:模擬和數字 電源電壓:1.8 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:40-WFQFN 裸露焊盤 供應商設備封裝:40-TQFN-EP（6x6） 包裝:托盤 |
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