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參數資料
| 型號： | AD9957 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 1 GSPS Quadrature Digital Upconverter with 18-Bit IQ Data Path and 14-Bit DAC |
| 中文描述： | 1 GSPS的正交數字上變頻器與18位智商數據路徑和14位DAC |
| 文件頁數： | 35/60頁 |
| 文件大小： | 840K |
| 代理商： | AD9957 |
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AD9957
PLL CHARGE PUMP
The charge pump current (I
CP
) is programmable to provide the
user with additional flexibility to optimize the PLL performance.
Table 9 lists the bit settings vs. the nominal charge pump
current.
Rev. 0 | Page 35 of 60
Table 9
.
PLL Charge Pump Current
I
CP
(CFR3<21:19>)
000
001
010
011
100
101
110
111
Charge Pump Current (I
CP
in μA)
212
237
262
287
312
337
363
387
EXTERNAL PLL LOOP FILTER COMPONENTS
The PLL_LOOP_FILTER pin provides a connection interface to
attach the external loop filter components. The ability to use
custom loop filter components gives the user more flexibility to
optimize the PLL performance. The PLL and external loop filter
components are shown in Figure 52.
PFD
CP
PLL_LOOP_FILTER
VCO
÷N
PLL OUT
PLL IN
AVDD
REFCLK PLL
2
R1
C1
C2
0
Figure 52. REFCLK PLL External Loop Filter
In the prevailing literature, this configuration yields a third-
order, Type II PLL. To calculate the loop filter component
values, begin with the feedback divider value (N), the gain of
the phase detector (K
D
), and the gain of the VCO (K
V
) based on
the programmed VCO SEL bit settings (see Table 1 for K
V
). The
loop filter component values depend on the desired open-loop
bandwidth (f
OL
) and phase margin (φ), as follows:
( )
tan
+
=
K
K
Nf
π
R1
V
D
OL
sin
( )
)
2
1
1
(7)
(
f
2
OL
V
D
N
K
K
C1
=
(8)
( )
( )
1
=
f
N
K
K
2
C2
OL
V
D
cos
sin
)
2
(9)
where:
K
D
equals the programmed value of I
CP
.
K
V
is taken from Table 1.
Ensure that proper units are used for the variables in Equation 7
through Equation 9. I
CP
must be in amps, not μA as appears in
Table 9; K
V
must be in Hz/V, not MHz/V as listed in Table 1; the
loop bandwidth (f
OL
) must be in Hz; the phase margin (φ) must
be in radians.
For example, suppose the PLL is programmed such that
I
CP
= 287 μA, K
V
= 625 MHz/V, and N = 25. If the desired loop
bandwidth and phase margin are 50 kHz and 45°, respectively,
the loop filter component values are R1 = 52.85 Ω, C1 =
145.4 nF, and C2 = 30.11 nF.
PLL LOCK INDICATION
When the PLL is in use, the PLL_LOCK pin provides an active
high indication that the PLL has locked to the REFCLK input
signal. When the PLL is bypassed the PLL_LOCK pin defaults
to Logic 0.
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| AD9957BSVZ | 功能描述:IC DDS 1GSPS 14BIT IQ 100TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數字合成 (DDS) 系列:- 產品變化通告:Product Discontinuance 27/Oct/2011 標準包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調節字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9957BSVZ-REEL | 功能描述:IC DDS 1GSPS 14BIT IQ 100TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數字合成 (DDS) 系列:- 產品變化通告:Product Discontinuance 27/Oct/2011 標準包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調節字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:帶卷 (TR) |
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