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參數資料
| 型號： | AD9995KCP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | 12-Bit CCD Signal Processor with Precision Timing ⑩ Generator |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, QCC56 |
| 封裝： | 8 X 8 MM, MO-220-VLLD-2, LFCSP-56 |
| 文件頁數： | 34/60頁 |
| 文件大小： | 1593K |
| 代理商： | AD9995KCP |
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AD9995
–34–
VD
HD
NOTES
1. SYNC RISING EDGE RESETS VD/HD AND COUNTERS TO ZERO.
2. SYNC POLARITY IS PROGRAMMABLE USING SYNCPOL REGISTER (ADDR 0x13).
3. DURING SYNC LOW, ALL INTERNAL COUNTERS ARE RESET AND VD/HD CAN BE SUSPENDED USING THE SYNCSUSPEND REGISTER (ADDR 0x14).
4. IF SYNCSUSPEND = 1, VERTICAL CLOCKS, H1–H2, AND RG ARE HELD AT THEIR DEFAULT POLARITIES.
5. IF SYNCSUSPEND = 0, ALL CLOCK OUTPUTS CONTINUE TO OPERATE NORMALLY UNTIL SYNC RESET EDGE.
SUSPEND
SYNC
H124, RG, V1–V4,
VSG, SUBCK
Figure 36. SYNC Timing to Synchronize AD9995 with External Timing
0
1
2
3
4
5
6
7
8
H-COUNTER
RESET
VD
NOTES
INTERNAL H-COUNTER IS RESET 17 CLI CYCLES AFTER THE HD FALLING EDGE (WHEN USING VDHDPOL = 0).
TYPICAL TIMING RELATIONSHIP: CLI RISING EDGE IS COINCIDENT WITH HD FALLING EDGE.
HD
CLI
X
X
X
X
X
X
X
X
X
H-COUNTER
(PIXEL COUNTER)
X
X
X
X
X
X
X
X
X
X
9
Figure 37. External VD/HD and Internal H-Counter Synchronization, Slave Mode
SYNC during Master Mode Operation
The SYNC input may be used at any time during operation to
resync the AD9995 counters with external timing, as shown in
Figure 36. The operation of the digital outputs may be suspended
during the SYNC operation by setting the SYNCSUSPEND
register (Addr. 0x14) to 1.
Power-Up and Synchronization in Slave Mode
The power-up procedure for Slave mode operation is the same
as the procedure described for Master mode operation, with two
exceptions:
Eliminate Step 9. Do not write the part into Master mode.
No SYNC pulse is required in Slave mode. Substitute Step 12
with starting the external VD and HD signals. This will syn-
chronize the part, allow Bank 1 register updates, and start the
timing operation.
When the AD9995 is used in Slave mode, the VD and HD inputs
are used to synchronize the internal counters. Following a falling
edge of VD, there will be a latency of 17 master clock cycles (CLI)
after the falling edge of HD until the internal H-counter will be
reset. The reset operation is shown in Figure 37.
STANDBY MODE OPERATION
The AD9995 contains three different standby modes
to optimize the overall power dissipation in a particular
application. Bits [1:0] of the OPRMODE register control
the power-down state of the device:
OPRMODE [1:0] = 00 = Normal Operation (Full Power)
OPRMODE[1:0] = 01 = Standby 1 Mode
OPRMODE[1:0] = 10 = Standby 2 Mode
OPRMODE[1:0] = 11 = Standby 3 Mode (Lowest Overall Power)
Table XIV summarizes the operation of each power-down
mode. Note that the OUT_CONTROL register takes priority
over the Standby 1 and Standby 2 modes in determining
the digital output states, but Standby 3 mode takes priority
over OUT_CONTROL. Standby 3 has the lowest power
consumption, and even shuts down the crystal oscillator cir-
cuit
between CLI and CLO. Therefore, if CLI and CLO are
being used with a crystal to generate the master clock, this
circuit will be powered down and there will be no clock signal.
When returning from Standby 3 mode to normal operation, the
timing core must be reset at least 500 μs after the OPRMODE
register is written to. This will allow sufficient time for the crys-
tal circuit
to settle.
REV. 0
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