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參數資料
| 型號： | ADATE207BBPZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | Quad Pin Timing Formatter |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA256 |
| 封裝： | ROHS COMPLIANT, MO-192-BAL-2, LBGA-256 |
| 文件頁數： | 7/36頁 |
| 文件大小： | 374K |
| 代理商： | ADATE207BBPZ |
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ADATE207
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Rev. 0 | Page 7 of 36
ADATE207
PATTERN DATA
PERIOD DATA
COMPARE FAILS
RECEIVE DATA
CH3 DCL I/F
CH2 DCL I/F
CH1 DCL I/F
CH0 DCL I/F
COMMAND/
STATUS BUS
TIME
MEASUREMENT
0
Figure 5. Connection Overview Diagram
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
2
4
6
8
10
12
14
16
18
20
1
3
5
7
9
11
13
15
17
19
BOTTOM
VIEW
(Not to Scale)
ADATE207
0
Figure 6. Ball Grid Array
Table 7. Pin Function Descriptions
Pin No.
B4, A4, C5, D6
Mnemonic
PAT_MASK[3:0]
Input/Output
1
I
Type
LVCMOS25
Description
Mask Failures. Used to mask failures on D3,
D2, D1 and D0 edges, respectively. Clocked
by MCLK.
Channel 0 Waveform Memory Address. Use
these pins to address waveform memory for
Channel 0. Clocked by MCLK.
Channel 1 Waveform Memory Address. Use
these pins to address waveform memory for
Channel 1. Clocked by MCLK.
Channel 2 Waveform Memory Address. Use
these pins to address waveform memory for
Channel 2. Clocked by MCLK.
Channel 3 Waveform Memory Address. Use
these pins to address waveform memory for
Channel 3. Clocked by MCLK.
Fails on D3, D2, D1 and D0 Edges for Channel 0.
Clocked by MCLK.
Fails on D3, D2, D1 and D0 Edges for Channel 1.
Clocked by MCLK.
Fails on D3, D2, D1 and D0 Edges for Channel 2.
Clocked by MCLK.
Fails on D3, D2, D1 and D0 Edges for Channel 3.
Clocked by MCLK.
DUT Capture Data from Channel 0. Clocked
by MCLK.
DUT Capture Data from Channel 1. Clocked
by MCLK.
DUT Capture Data from Channel 2. Clocked
by MCLK.
DUT Capture Data from Channel 3. Clocked
by MCLK.
T3, U1, U2, T4, U3, V4, U5, W4
PAT_PATDATA_0[7:0]
I
LVCMOS25
B5, A5, C6, B6, A6, C7, B7, D8
PAT_PATDATA_1[7:0]
I
LVCMOS25
W212, V12, Y13, U12, W13,
V13, Y14, W14
PAT_PATDATA_2[7:0]
I
LVCMOS25
A16, B16, D15, C16, A17,
B17, D16, C17
PAT_PATDATA_3[7:0]
I
LVCMOS25
Y4, W5, V6
PAT_FAIL_0[3:0]
O
LVCMOS25
B8, A8, B9, B10
PAT_FAIL_1[3:0]
O
LVCMOS25
V8, W8, W9, Y9
PAT_FAIL_2[3:0]
O
LVCMOS25
B12, C12, B13, A14
PAT_FAIL_3[3:0]
O
LVCMOS25
W6, Y6, W7, Y7
PAT_DUTDATA_0[3:0]
O
LVCMOS25
C10, A11, B11, A12
PAT_DUTDATA_1[3:0]
O
LVCMOS25
V10, W10, Y10, W11
PAT_DUTDATA_2[3:0]
O
LVCMOS25
B14, C14, A15, B15
PAT_DUTDATA_3[3:0]
O
LVCMOS25
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