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參數(shù)資料
| 型號(hào)： | ADC912AFS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | CMOS Microprocessor-Compatible 12-Bit A/D Converter |
| 中文描述： | 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO24 |
| 封裝： | SOIC-24 |
| 文件頁數(shù)： | 13/16頁 |
| 文件大小： | 237K |
| 代理商： | ADC912AFS |
REV. B
ADC912A
–13–
SLOW-MEMORY MODE OPERATION USING WAIT
STATES
The WAIT state feature of the TMS32020 can also be used to
operate the ADC912A in the Slow-Memory mode. This is
accomplished by driving the clock input of the 7474 flip-flop in
Figure 23, from the BUSY output of the ADC912A, instead of
the CLK OUT 1 of the TMS32020. Once a conversion has
started the READY input of the TMS32020 is not released until
the ADC912A completes its 12-bit A/D conversion. This stops
the TMS32020 during the conversion process reducing micro-
processor system noise generation. Another advantage for the
system software is the single instruction IN MEM, PA used to
start, process, and read the results of the A/D conversion. This
makes the software code more transportable between systems
operating at different clock speeds. The disadvantage is some
loss in instruction processing time.
ADDRESS
DECODE
EN
ADDRESS BUS
DATA BUS
D
15
D
0
D
11
D
0/8
A
0
A
15
HBEN
ADC912A
*
TMS32020
CS
RD
IS
*
ESSENTIAL INTERFACE CIRCUITRY SHOWN FOR CLARITY
READY
R/W
BUSY
CK
7474
D
Q
CLR
CLK OUT
1
20MHz
2/CLK IN
"1"
SLOW-MEMORY
MODE
ROM MODE
(ONE WAIT STATE)
Figure 23. ADC912A to TMS32020 Interface Using Wait
States
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