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參數(shù)資料
| 型號： | ADC912AFS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | CMOS Microprocessor-Compatible 12-Bit A/D Converter |
| 中文描述： | 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO24 |
| 封裝： | SOIC-24 |
| 文件頁數(shù)： | 5/16頁 |
| 文件大小： | 237K |
| 代理商： | ADC912AFS |
REV. B
ADC912A
–5–
WAFER TEST LIMITS
ADC912AG
Limit
±
1
±
1
±
8
±
8
4/6
2.4
0.8
±
1
4
0.4
7
5
Parameter
Symbol
Conditions
Unit
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Gain Error
Analog Input Resistance
Logic Input High Voltage
Logic Input Low Voltage
Logic Input Current
Logic Output High Voltage
Logic Output Low Voltage
Positive Supply Current
Negative Supply Current
INL
DNL
V
ZSE
G
FSE
R
AIN
V
INH
V
INL
I
IN
V
OH
V
OL
I
DD
I
SS
LSB max
LSB max
LSB max
LSB max
k
min/max
V min
V max
μ
A max
V min
V max
mA max
mA max
Guaranteed by Design
CS
,
RD
, HBEN
CS
,
RD
, HBEN
CS
,
RD
, HBEN
I
SOURCE
= 0.2 mA
I
SINK
= 1.6 mA
V
DD
= +5 V,
CS
=
RD
= V
DD
, A
IN
= +10 V
V
SS
= –12 V,
CS
=
RD
= V
DD
, A
IN
= +10 V
NOTE
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
(@ V
DD
= +5 V, V
SS
=
–
12 V or
–
15 V, V
REF
=
–
5 V, A
IN
= 0 V to 10 V, and T
A
= 25 C, unless otherwise noted.)
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
NC
NC
NC
NC
NC
NC
NC
C1
C2
C1
C2
+
+
C1
C2
C1
C2
+
+
10V
–
5V
+5V
–
15V
R
R
R
R
R
R
R
R = 10
C1 = 0.01 F
C2 = 4.7 F
NC = NO CONNECT
POWER SUPPLY SEQUENCE:
+5V,
–
15V,
–
5V, +10V
ADC912A
TOP VIEW
(Not to Scale)
Figure 9. Burn-In Circuit
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