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參數資料
| 型號： | ADCMP580BCP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 運動控制電子 |
| 英文描述： | Ultrafast SiGe Voltage Comparator |
| 中文描述： | COMPARATOR, 5000 uV OFFSET-MAX, QCC16 |
| 封裝： | MO-220-VEED-2, LFCSP-16 |
| 文件頁數： | 13/16頁 |
| 文件大小： | 284K |
| 代理商： | ADCMP580BCP |
Preliminary Technical Data
ADCMP580/ADCMP581/ADCMP582
TIMING INFORMATION
Figure 26 shows the ADCMP580/ADCMP581/ADCMP582 compare and latch timing relationships. Table 4 provides a definition of the
terms shown in the figure.
Rev. PrA | Page 13 of 16
50%
50%
V
N
± V
OS
50%
DIFFERENTIAL
INPUT VOLTAGE
LATCH ENABLE
Q OUTPUT
Q OUTPUT
LATCH ENABLE
t
H
t
PDL
t
PDH
t
PLOH
t
PLOL
t
R
t
F
V
N
V
OD
t
S
t
PL
0
Figure 26. Comparator Timing Diagram
Table 4. Timing Descriptions
Symbol
Timing
t
PDH
Input to output high
delay
t
PDL
Input to output low
delay
t
PLOH
Latch enable to output
high delay
t
PLOL
Latch enable to output
low delay
t
H
Minimum hold time
Description
Propagation delay measured from the time the input signal crosses the reference (± the input offset
voltage) to the 50% point of an output low-to-high transition.
Propagation delay measured from the time the input signal crosses the reference (± the input offset
voltage) to the 50% point of an output high-to-low transition.
Propagation delay measured from the 50% point of the Latch Enable signal low-to-high transition to
the 50% point of an output low-to-high transition.
Propagation delay measured from the 50% point of the Latch Enable signal low-to-high transition to
the 50% point of an output high-to-low transition.
Minimum time after the negative transition of the Latch Enable signal that the input signal must
remain unchanged to be acquired and held at the outputs.
Minimum time that the Latch Enable signal must be high to acquire an input signal change.
t
PL
Minimum latch enable
pulse width
Minimum setup time
t
S
Minimum time before the negative transition of the Latch Enable signal that an input signal change
must be present to be acquired and held at the outputs.
Amount of time required to transition from a low to a high output as measured at the 20% and 80%
points.
Amount of time required to transition from a high to a low output as measured at the 20% and 80%
points.
Difference between the input voltages V
P
and V
N
.
t
R
Output rise time
t
F
Output fall time
V
OD
Voltage overdrive
相關PDF資料 |
PDF描述 |
|---|---|
| ADCMP581BCP | Ultrafast SiGe Voltage Comparator |
| ADCMP603BCPZ-WP | Rail-to-Rail, Very Fast, 2.5 V to 5.5 V, Single-Supply TTL/CMOS Comparator |
| ADCMP603 | Rail-to-Rail, Very Fast, 2.5 V to 5.5 V, Single-Supply TTL/CMOS Comparator |
| ADCMP603BCPZ-R2 | Rail-to-Rail, Very Fast, 2.5 V to 5.5 V, Single-Supply TTL/CMOS Comparator |
| ADCMP603BCPZ-R7 | Rail-to-Rail, Very Fast, 2.5 V to 5.5 V, Single-Supply TTL/CMOS Comparator |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ADCMP580BCP-R2 | 制造商:Analog Devices 功能描述:Comparator Single ±5.5V 16-Pin LFCSP EP T/R |
| ADCMP580BCP-RL7 | 制造商:Analog Devices 功能描述:Comparator Single ±5.5V 16-Pin LFCSP EP T/R |
| ADCMP580BCP-WP | 制造商:Analog Devices 功能描述:Comparator Single ±5.5V 16-Pin LFCSP EP 制造商:Analog Devices 功能描述:IC ((NS)) |
| ADCMP580BCPZ-R2 | 功能描述:IC COMPARATOR CML UFAST 16-LFCSP RoHS:是 類別:集成電路 (IC) >> 線性 - 比較器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 類型:通用 元件數:1 輸出類型:CMOS，推挽式，滿擺幅，TTL 電壓 - 電源，單路/雙路(±):2.5 V ~ 5.5 V，±1.25 V ~ 2.75 V 電壓 - 輸入偏移（最小值）:5mV @ 5.5V 電流 - 輸入偏壓（最小值）:1pA @ 5.5V 電流 - 輸出（標準）:- 電流 - 靜態（最大值）:24µA CMRR, PSRR（標準）:80dB CMRR，80dB PSRR 傳輸延遲（最大）:450ns 磁滯:±3mV 工作溫度:-40°C ~ 85°C 封裝/外殼:6-WFBGA，CSPBGA 安裝類型:表面貼裝 包裝:管件 其它名稱:Q3554586 |
| ADCMP580BCPZ-RL7 | 功能描述:IC COMPARATOR CML UFAST 16-LFCSP RoHS:是 類別:集成電路 (IC) >> 線性 - 比較器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 類型:通用 元件數:1 輸出類型:CMOS，推挽式，滿擺幅，TTL 電壓 - 電源，單路/雙路(±):2.5 V ~ 5.5 V，±1.25 V ~ 2.75 V 電壓 - 輸入偏移（最小值）:5mV @ 5.5V 電流 - 輸入偏壓（最小值）:1pA @ 5.5V 電流 - 輸出（標準）:- 電流 - 靜態（最大值）:24µA CMRR, PSRR（標準）:80dB CMRR，80dB PSRR 傳輸延遲（最大）:450ns 磁滯:±3mV 工作溫度:-40°C ~ 85°C 封裝/外殼:6-WFBGA，CSPBGA 安裝類型:表面貼裝 包裝:管件 其它名稱:Q3554586 |
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