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參數資料
| 型號： | ADF4193BCPZ-RL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | XO, clock |
| 英文描述： | Low Phase Noise, Fast Settling PLL Frequency Synthesizer |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 3500 MHz, QCC32 |
| 封裝： | 5 X 5 MM, ROHS COMPLIANT, MO-220VHHD-2, LFCSP-32 |
| 文件頁數： | 22/28頁 |
| 文件大小： | 437K |
| 代理商： | ADF4193BCPZ-RL7 |
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ADF4193
PROGRAMMING
The ADF4193 can synthesize output frequencies with a channel
step or resolution that is a fraction of the input reference frequency.
For a given input reference frequency and a desired output
frequency step, the first choice to make is the PFD reference
frequency and the MOD. Once these are chosen, the desired
output frequency channels are set by programming the INT
and FRAC values.
Rev. B | Page 22 of 28
WORKED EXAMPLE
In this example of a GSM900 RX system, it is required to
generate RF output frequencies with channel steps of 200 kHz.
A 104 MHz reference frequency input (REF
IN
) is available. The
R divider setting that set the PFD reference is shown in
Equation 1.
F
PFD
=
REF
IN
× [(1 +
D
)/(
R
× (1 +
T
))]
(1)
where:
REF
IN
is the input reference frequency.
D
is the doubler enable bit (0 or 1).
R
is the 4-bit R counter code (0…15).
T
is the REF/2 bit (0 or 1).
The maximum PFD reference frequency of 26 MHz is chosen
and the following settings are programmed to give an R divider
value of 4:
Doubler enable = 0
R = 2
REF/2 = 1
Next, the modulus is chosen to allow fractional steps of 200 kHz.
MOD
= 26 MHz/200 kHz = 130
(2)
Once the channel step is defined, the following equation shows
how output frequency channels are programmed:
RF
OUT
= [
INT
+ (
FRAC
/
MOD
] × [
F
PFD
]
(3)
where:
RF
OUT
is the desired RF output frequency.
INT
is the integer part of the division.
FRAC
is the numerator part of the fractional division.
MOD
is the modulus or denominator part of the fractional
division.
For example, the frequency channel at 962.4 MHz is synthesized
by programming the following values:
INT = 37
FRAC = 2
SPUR MECHANISMS
The Fractional Spurs, Integer Boundary Spurs, and Reference
Spurs sections describe the three different spur mechanisms
that arise with a fractional-N synthesizer and how the ADF4193
can be programmed to minimize them.
Fractional Spurs
The fractional interpolator in the ADF4193 is a third-order, Σ-Δ
modulator (SDM) with a modulus (MOD) that is programmable to
any integer value from 13 to 4095. If dither is enabled, then the
minimum allowed value of MOD is 50. The SDM is clocked at
the PFD reference rate (f
PFD
) that allows PLL output frequencies
to be synthesized at a channel step resolution of f
PFD
/MOD.
With dither turned off, the quantization noise from the Σ-Δ
modulator appears as fractional spurs. The interval between
spurs is
f
PFD
/
L
, where
L
is the repeat length of the code sequence
in the digital Σ-Δ modulator. For the third-order modulator
used in the ADF4193, the repeat length depends on the value of
MOD, as shown in Table 7.
Table 7. Fractional Spurs with Dither Off
Condition (Dither Off)
If MOD is divisible by 2,
but not 3
If MOD is divisible by 3,
but not 2
If MOD is divisible by 6
Otherwise
Repeat Length
2 × MOD
Spur Interval
Channel step/2
3 × MOD
Channel step/3
6 × MOD
MOD
Channel step/6
Channel step
With dither enabled, the repeat length is extended to 2
21
cycles,
regardless of the value of MOD, which makes the quantization
error spectrum look like broadband noise. This can degrade the
in-band phase noise at the PLL output by as much as 10 dB.
Therefore, for the lowest noise, dither off is a better choice,
particularly when the final loop BW is low enough to attenuate
even the lowest frequency fractional spur. The wide loop
bandwidth range available with the ADF4193 makes this
possible in most applications.
Integer Boundary Spurs
Another mechanism for fractional spur creation involves
interactions between the RF VCO frequency and the reference
frequency. When these frequencies are not integer related, spur
sidebands appear on the VCO output spectrum at an offset
frequency that corresponds to the beat note or difference
frequency between an integer multiple of the reference and the
VCO frequency.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| ADF4193SP1BCPZ | 制造商:Analog Devices 功能描述: |
| ADF4193SP1BCPZ-RL7 | 制造商:Analog Devices 功能描述: |
| ADF4193SP2BCPZ-RL7 | 制造商:Analog Devices 功能描述: |
| ADF4193WCCPZ-RL7 | 功能描述:IC PLL FREQ SYNTHESIZER 32LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發生器，PLL，頻率合成器 系列:- 標準包裝:2,000 系列:- 類型:PLL 時鐘發生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數:1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應商設備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
| ADF4196 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Low Phase Noise, Fast Settling, 6 GHz |
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