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| 型號： | ADM1026 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Complete Thermal and System Management Controller |
| 中文描述： | 完整的熱和系統管理控制器 |
| 文件頁數： | 46/56頁 |
| 文件大小： | 634K |
| 代理商： | ADM1026 |
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ADM1026
Rev. A | Page 46 of 56
Table 49. Register 24h, Status Register 5 (Power-On Default 00h)
Bit Name
R/W
1
0
GPIO0 Status = 0
R
Description
When GPIO0 is configured as an input, this bit is set when GPIO0 is asserted. (Asserted may be
active high or active low depending on setting of Bit 1 in GPIO Configuration Register 1.)
When GPIO0 is configured as an output, setting this bit asserts GPIO0. (Asserted may be active high
or active low depending on setting of Bit 1 in GPIO Configuration Register 1.)
When GPIO1 is configured as an input, this bit is set when GPIO1 is asserted. (Asserted may be
active high or active low depending on setting of Bit 3 in GPIO Configuration Register 1.)
When GPIO1 is configured as an output, setting this bit asserts GPIO1. (Asserted may be active high
or active low depending on setting of Bit 3 in GPIO Configuration Register 1.)
When GPIO2 is configured as an input, this bit is set when GPIO2 is asserted. (Asserted may be
active high or active low depending on setting of Bit 5 in GPIO Configuration Register 1.)
When GPIO2 is configured as an output, setting this bit asserts GPIO2. (Asserted may be active high
or active low depending on setting of Bit 5 in GPIO Configuration Register 1.)
When GPIO3 is configured as an input, this bit is set when GPIO3 is asserted. (Asserted may be
active high or active low depending on setting of Bit 7 in GPIO Configuration Register 1.)
When GPIO3 is configured as an output, setting this bit asserts GPIO3. (Asserted may be active high
or active low depending on setting of Bit 7 in GPIO Configuration Register 1.)
When GPIO4 is configured as an input, this bit is set when GPIO4 is asserted. (Asserted may be
active high or active low depending on setting of Bit 1 in GPIO Configuration Register 2.)
When GPIO4 is configured as an output, setting this bit asserts GPIO4. (Asserted may be active high
or active low depending on setting of Bit 1 in GPIO Configuration Register 2.)
When GPIO5 is configured as an input, this bit is set when GPIO5 is asserted. (Asserted may be
active high or active low depending on setting of Bit 3 in GPIO Configuration Register 2.)
When GPIO5 is configured as an output, setting this bit asserts GPIO5. (Asserted may be active high
or active low depending on setting of Bit 3 in GPIO Configuration Register 2.)
When GPIO6 is configured as an input, this bit is set when GPIO6 is asserted. (Asserted may be
active high or active low depending on setting of Bit 5 in GPIO Configuration Register 2.)
When GPIO6 is configured as an output, setting this bit asserts GPIO6. (Asserted may be active high
or active low depending on setting of Bit 5 in GPIO Configuration Register 2.)
When GPIO7 is configured as an input, this bit is set when GPIO7 is asserted. (Asserted may be
active high or active low depending on setting of Bit 7 in GPIO Configuration Register 2.)
When GPIO7 is configured as an output, setting this bit asserts GPIO7. (Asserted may be active high
or active low depending on setting of Bit 7 in GPIO Configuration Register 2.)
R/W
1
GPIO1 Status = 0
R
R/W
2
GPIO2 Status = 0
R
R/W
3
GPIO3 Status = 0
R
R/W
4
GPIO4 Status = 0
R
R/W
5
GPIO5 Status = 0
R
R/W
6
GPIO6 Status = 0
R
R/W
7
GPIO7 Status = 0
R
R/W
1
GPIO status bits can be written only when a GPIO pin is configured as output. Read-only otherwise.
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