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參數(shù)資料
| 型號(hào)： | ADM5104 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Four-channel FastFast Ethernet 110Base-TX Transceiver(四通道110Base-TX快速以太網(wǎng)收發(fā)器) |
| 中文描述： | 四通道FastFast以太網(wǎng)110Base -得克薩斯州收發(fā)器（四通道110Base -得克薩斯州快速以太網(wǎng)收發(fā)器） |
| 文件頁(yè)數(shù)： | 2/8頁(yè) |
| 文件大小： | 75K |
| 代理商： | ADM5104 |
–2–
REV. 0
ADM5104–SPECIFICATIONS
PRELIMINARY
DATA
TECHNICAL
150
1000
2
CC
– 1
0, 20, 40
5
2.5
3.0
4.0
750
Parameter
Min
T yp
Max
Units
T est Conditions/Comments
RECEIVER
Input Signal Range
764
mV p-p
V p-p
V
k
Bit Periods
ms
0 to 110 M UT P#5 (140)
1.06
2.1
Differential Input Voltage
Differential Input Voltage
Differential Input Resistance
10.0
T ransitionless Data Run
Equalizer T ime Constant
400
1000
Ceq-0.1
μ
F
RECEIVER OUT PUT LEVELS
Output Logic High, V
OH
–1.2
PECL V
PECL V
PECL V
PECL V
PECL V
PECL V
ns
RDn+, RDn–
–1.0
–0.7
Output Logic Low, V
OL
–2.0
RDn+, RDn–
–1.8
–1.7
Output Drive
Rise and Fall T imes
50
1.0
Loads, No Cap
SIGNAL DET ECT
T rip Level
200
mV p-p
mV p-p
mV p-p
2
23
– 1 PRN, 0 M Cable
350
750
Release Level
2
23
– 1 PRN, 0 M Cable
mV p-p
30 M Cable From Receiver Input to Active/Inactive
SDn+, SDn–
1000
Response T ime
SDOUT Output Logic High, V
OH
12.9
μ
s
PECL V
PECL V
PECL V
PECL V
PECL V
–1.2
–1.0
–0.7
SDOUT Output Logic Low, V
OL
–2.0
SDn+, SDn–
–1.8
–1.7
T RANSMIT T ER LINE DRIVER
Differential Input
mV
mV
V
V
mA
%
%
ns
ns
ps
Output Current Variation < 1%
Common-Mode Input Voltage
Output Current Levels MLT 3
Output Current Variation
Common-Mode Current
Rise and Fall T imes
Rise and Fall T imes
Output Jitter
Into 50
1% Resistor to Ground at RSET n = 2.2 k
Percentage of Output Drive Current with 50
Loads
10 %–90% MLT 3 Levels 100
Loads at T + and T –
10 %–90% MLT 3 Levels 100
through X former Loads
INPUT CONT ROL SIGNALS
Input Logic Low, V
IL
Input Logic High, V
IH
LPBCK On to RECEIVER Output Delay
LPBCK Off to RECEIVER Output Delay
LPBCK On to X MIT T ER Output Balance
LPBCK Off to X MIT T ER Output Active
MLT 3_DIS On to X MIT T ER Output Off
MLT 3_DIS Off to X MIT T ER Output Active
0.8
V
V
ns
ns
ns
ns
ns
ns
LPBCK n, MLT 3_DISn
2
150
150
150
150
150
350
Filtered Input Pin
Filtered Input Pin
Filtered Input Pin
Filtered Input Pin
Filtered Input Pin
Filtered Input Pin
POWER REQUIREMENT S
Power Voltage Supply
Power Voltage Supply
T otal Power In Chip
T ypical Power In Chip
4.5
V
V
Watts
Watts
mA
mA
mA
mA
5.5
1.6
125 MHz @ 5.5 V
125 MHz @ 25
°
C, V
CC
= 5.0 V
From VCC into Chip Core
From VCC into PECL Outputs
From Chip Core to GND
From X mitter Line Driver Outputs to GND
1.3
80
160
80
160
OPERAT ING T EMPERAT URE RANGE
0
+70
°
C
Ambient
(EVCCn = TVCCn = RVCCn = +5.0 V, T
A
+ T
MN
to T
MAX
, unless otherwse noted)
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