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參數資料
| 型號： | ADM5104 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Four-channel FastFast Ethernet 110Base-TX Transceiver(四通道110Base-TX快速以太網收發器) |
| 中文描述： | 四通道FastFast以太網110Base -得克薩斯州收發器（四通道110Base -得克薩斯州快速以太網收發器） |
| 文件頁數： | 8/8頁 |
| 文件大小： | 75K |
| 代理商： | ADM5104 |
ADM5104
–8–
REV. 0
C
P
PRELIMINARY
of a 3.3 V ASIC using either ac coupling or dc coupling (Figures
4a and 4b). T hese schemes assume that the PECL output drives
the “long” portion of the transmission line. T he passive shifting
and termination network is located as close to the LVDS input
as possible.
TECHNICAL
80-T erminal Plastic T hin Quad Flatpack (T QFP)
(ST -80)
SEATING
PLANE
0.063 (1.60)
MAX
0.030 (0.75)
0.020 (0.50)
0.004
(0.10)
MAX
0.057 (1.45)
0.053 (1.35)
0.006 (0.15)
0.002 (0.05)
0.014 (0.35)
0.010 (0.25)
0.640 (16.25)
0.620 (15.75)
0.553 (14.05)
0.549 (13.95)
0.486 (12.35) TYP
0
0
0
0
1
20
21
41
40
60
61
80
0
TOP VIEW
(PINS DOWN)
0.029 (0.73)
0.022 (0.57)
OUT LINE DIME NSIONS
Dimensions shown in inches and (mm).
PE CL interface to IE E E LVDS levels
T he ADM5104 high speed inputs and outputs operate at PECL
levels. ASICs in a 3.3 V CMOS that use IEEE LVDS levels
(Low Voltage Differential Signal) for its high speed digital out-
puts and inputs should refer to the following paragraphs and to
Figures 3 and 4 for the description of the interface to the
ADM5104.
LVDS to PE CL Conversion
LVDS levels from the ASIC can be shifted to PECL levels to the
ADM5104 using capacitive coupling (Figure 3). T his scheme
assumes the LVDS output drives the “long” portion on the
transmission line. T he passive shifting and termination network
is located as close to the PECL input as possible.
TRANSMISSION LINE
(50
) PCB TRACE)
100
100nF
100nF
1k
1k
160
V
CC
= 5V
470
10nF
TDn+ (PECL)
TDn– (PECL)
ADM5104
LVDS_OUT
LVDS_OUT
NOTE:
ALL COMPONENTS SHOULD
BE PLACED AS CLOSE TO THE
ADM5104 DESTINATION PINS
AS POSSIBLE TO ENSURE
PROPER IMPEDANCE
MATCHING.
BRIEF ANALYSIS:
1. TERMINATION IS DONE BY THE 100
RESISTOR BETWEEN THE DIFFERENTIAL LINES.
2. THE 100nF CAPACITORS PROVIDE AC COUPLING TO THE PHY ASIC OUTPUT.
3. THE RESISTOR DIVIDER GENERATES THE NEW OFFSET VOLTAGE (VBB, IN CENTER
BETWEEN PECL VIH AND VIL) OF APPROXIMATELY 3.7V.
4. THE TWO 1k
RESISTORS ARE USED FOR DECOUPLING THE TWO SIGNALS.
5. PECL COMMON-MODE VOLTAGE SUPPLIED EXTERNALLY.
COMPONENTS ARE NOT REQUIRED.
Figure 3. LVDS to PECL Conversion
PE CL to LVDS Conversion
PECL levels from the ADM5104 can be shifted to LVDS levels
TRANSMISSION LINE
(50
) PCB TRACE)
120
100nF
100nF
1k
1k
220
V
CC
= 3.3V
120
10nF
LVDS_IN
LVDS_IN
NOTE:
ALL COMPONENTS
SHOULD BE PLACED
AS CLOSE TO THE
ADM5104 DESTINATION PINS
AS POSSIBLE TO ENSURE
PROPER IMPEDANCE MATCHING.
BRIEF ANALYSIS:
1. TERMINATION IS DONE BY A PARALLEL THEVEVIN SCHEME.
2. THE 100nF CAPACITORS PROVIDE AC COUPLING.
RDn–
RDn+
ADM5104
120
82
82
V
CC
= 5V
V
CC
= 5V
a.
TRANSMISSION LINE
(50
) PCB TRACE)
+5V
47
47
82
PECL 5V (V
CC
)
LVDS_IN
LVDS_IN
NOTE:
ALL COMPONENTS SHOULD
BE PLACED AS CLOSE TO THE
PHY ASIC DESTINATION PINS
AS POSSIBLE TO ENSURE
PROPER IMPEDANCE
MATCHING.
BRIEF ANALYSIS:
1. SHIFTING NETWORK BASED ON THEVENIN SCHEME WITH LOWER RESISTOR
REPLACED BY DIVIDER.
2. COMMON MODE VOLTAGE TRANSFORMED FROM 3.7V DOWN TO 1.4V.
3. DIFFERENTIAL VOLTAGE SWING ATTENUATED FROM 600mV MINIMUM (PECL)
TO 220mV MINIMUM FOR LVDS.
ADM5104
RDn+
RDn–
82
0.01μF
82
82
FERRITE BEAD
b.
Figure 4. PECL to LVDS Conversion
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