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參數資料
| 型號： | ADMCF340BST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數字信號處理 |
| 英文描述： | DashDSPTM 64-Lead Flash Mixed-Signal DSP with Enhanced Analog Front End |
| 中文描述： | 0-BIT, 10 MHz, OTHER DSP, PQFP64 |
| 封裝： | PLASTIC, LQFP-64 |
| 文件頁數： | 36/40頁 |
| 文件大小： | 415K |
| 代理商： | ADMCF340BST |
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REV. 0
ADMCF340
–36–
ADC MUX
CONTROL
0 = BOOT MODE
1 = UART MODE
SPORT1 MODE
SELECT
0 = DISABLE
1 = ENABLE
PWMSYNC
INTERRUPT
0 = DISABLE
1 = ENABLE
PWMTRIP
I
NTERRUPT
0
0
0
0
0
0
0
0
0
0
0
SYSSTAT (R)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0 = LOW
1 = HIGH
DM (0x2016)
0 = NORMAL
1 = WATCHDOG RESET
OCCURRED
PWMTRIP
PIN STATUS
WATCHDOG
STATUS
PWM TIMER
STATUS
0 = 1ST HALF OF PWM
CYCLE
1 = 2ND HALF OF PWM
CYCLE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MODECTRL (R/W)
9
8
DM (0x2015)
0 = SINGLE UPDATE MODE
1 = DOUBLE UPDATE MODE
15
14
13
12
11
10
7
6
5
4
3
2
1
0
ADC MUX CONTROL
*
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
IRQFLAG (R)
PWMTRIP
INTERRUPT
PWMSYNC INTERRUPT
DM (0x2017)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
WDTIMER (W)
DM (0x2018)
0
1
0 = NO INTERRUPT
1 = INTERRUPT OCCURRED
PWM UPDATE
MODE SELECT
ADC
COUNTER
0 = CLKIN RATE
1 = CLKOUT RATE
AUX PWM
MODE SELECT
CHANNEL 1
SELECTION
0 = OFFSET MODE
1 = INDEPENDENT MODE
0 = I
1 = VOLTAGE
CHANNEL 2
SELECTION
0 = I
1 = VOLTAGE
CHANNEL 3
SELECTION
0 = I
1 = VOLTAGE
SPORT 0
MODE SELECT
0 = SPORT MODE
1 = UART MODE
SPORT 0
SPI MODE
0 = SPORT
1 = SP1 MODE
SPI CLOCK
POLARITY
0 = STANDARD
1 = REVERSE
SPI CLOCK
PHASE
0 = PHA0
1 = PHA1
ADC MUX CONTROL
*
Figure 28. Configuration of Status/Control Registers
Default bit values are shown; if no value is shown, the bit field is undefined at reset.
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