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參數資料
| 型號： | ADMCF340BST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數字信號處理 |
| 英文描述： | DashDSPTM 64-Lead Flash Mixed-Signal DSP with Enhanced Analog Front End |
| 中文描述： | 0-BIT, 10 MHz, OTHER DSP, PQFP64 |
| 封裝： | PLASTIC, LQFP-64 |
| 文件頁數： | 38/40頁 |
| 文件大小： | 415K |
| 代理商： | ADMCF340BST |
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REV. 0
ADMCF340
–38–
SPORT1 RECEIVE OR
IRQ0
IFC
INTERRUPT FORCE
INTERRUPT CLEAR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TIMER
SOFTWARE 0
SOFTWARE 1
IRQ2
TIMER
SOFTWARE 0
SOFTWARE 1
IRQ2
DSP REGISTER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SPORT1 TRANSMIT OR
IRQ1
SPORT1 RECEIVE OR
IRQ0
SPORT1 TRANSMIT OR
IRQ1
1
1
0
0
0
IRQ0
SENSITIVITY
0 = LEVEL
1 = EDGE
ICNTL
2
IRQ1
SENSITIVITY
IRQ2
SENSITIVITY
INTERRUPT NESTING
0 = DISABLE
1 = ENABLE
DSP REGISTER
4
3
1
0
IMASK (R/W)
8
PERIPHERAL (OR
IRQ2
)
TIMER
SPORT1 RECEIVE
(OR
IRQ0
)
SPORT1 TRANSMIT
(OR
IRQ1
)
SOFTWARE 0
SOFTWARE 1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
DSP REGISTER
0 = DISABLE
(MASK)
1 = ENABLE
0 = DISABLE
(MASK)
1 = ENABLE
15
14
13
12
11
10
9
7
6
5
4
3
2
1
0
SPORT0 TRANSMIT
SPORT0 RECEIVE
SPORT0 RECEIVE
SPORT0 TRANSMIT
SPORT0 TRANSMIT
SPORT0 RECEIVE
Figure 29. Configuration of Interrupt Control Registers
Default bit values are shown; if no value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray field—these
bits should always be written as shown.
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