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參數資料
| 型號： | ADN2819ACPZ-CML-RL1 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 運動控制電子 |
| 英文描述： | Multirate to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp |
| 中文描述： | 多速率為2.7 Gb / s的集成時鐘和數據恢復芯片限幅放大器 |
| 文件頁數： | 16/24頁 |
| 文件大小： | 570K |
| 代理商： | ADN2819ACPZ-CML-RL1 |
ADN2819
Rev. B | Page 16 of 24
50
50
QUANTIZER
+
ADN2819
VREF
NIN
PIN
50
50
VCC
TDINP/N
LOOPEN
BYPASS
CDR
RETIMED
DATA
CLK
0
1
1
0
DATAOUTP/N
CLKOUTP/N SQUELCH
FROM
QUANTIZER
OUTPUT
0
Figure 21. Test Modes
SQUELCH MODE
When the squelch input is driven to a TTL high state, the clock
and data outputs are set to the zero state to suppress down-
stream processing. If desired, this pin can be directly driven by
the LOS (loss of signal) detector output (SDOUT). If the
squelch function is not required, the pin should be tied to VEE.
TEST MODES: BYPASS AND LOOPBACK
When the bypass input is driven to a TTL high state, the
quantizer output is connected directly to the buffers driving the
data out pins, thus bypassing the clock recovery circuit (see
Figure 21). This feature can help the system deal with
nonstandard bit rates.
The loopback mode can be invoked by driving the LOOPEN
pin to a TTL high state, which facilitates system diagnostic
testing. This connects the test inputs (TDINP/N) to the clock
and data recovery circuit (per Figure 21). The test inputs have
internal 50 terminations, and can be left floating when not in
use. TDINP/N are CML inputs and can only be dc-coupled
when being driven by CML outputs. The TDINP/N inputs must
be ac-coupled if driven by anything other than CML outputs.
Bypass and loopback modes are mutually exclusive: only one of
these modes can be used at any given time. The ADN2819 is put
into an indeterminate state if both the BYPASS and LOOPEN
pins are set to Logic 1 at the same time.
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