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參數(shù)資料
| 型號(hào)： | ADN2819ACPZ-CML-RL1 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 運(yùn)動(dòng)控制電子 |
| 英文描述： | Multirate to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp |
| 中文描述： | 多速率為2.7 Gb / s的集成時(shí)鐘和數(shù)據(jù)恢復(fù)芯片限幅放大器 |
| 文件頁數(shù)： | 5/24頁 |
| 文件大小： | 570K |
| 代理商： | ADN2819ACPZ-CML-RL1 |
ADN2819
Parameter
Setup Time
Hold Time
REFCLK DC INPUT CHARACTERISTICS
Input Voltage Range
Peak-to-Peak Differential Input
Common-Mode Level
TEST DATA DC INPUT CHARACTERISTICS
4
(TDINP/N)
Peak-to-Peak Differential Input Voltage
LVTTL DC INPUT CHARACTERISTICS
Input High Voltage
Input Low Voltage
Input Current
Input Current (SEL0 and SEL1 Only)
5
LVTTL DC OUTPUT CHARACTERISTICS
Output High Voltage
Output Low Voltage
Rev. B | Page 5 of 24
Conditions
T
S
(See Figure 3)
OC-48
GbE
OC-12
OC-3
T
H
(See Figure 3)
OC-48
GbE
OC-12
OC-3
@ REFCLKP or REFCLKN
DC-coupled, single-ended
CML inputs
V
IH
V
IL
V
IN
= 0.4 V or V
IN
= 2.4 V
V
IN
= 0.4 V or V
IN
= 2.4 V
V
OH
, I
OH
= –2.0 mA
V
OL
, I
OL
= +2.0 mA
Min
140
350
750
3145
150
350
750
3150
0
100
2.0
–5
–5
2.4
Typ
VCC/2
0.8
V
Max
VCC
0.8
+5
+50
0.4
Unit
ps
ps
ps
ps
ps
ps
ps
ps
V
mV
V
V
V
μA
μA
V
V
1
PIN and NIN should be differentially driven, ac-coupled for optimum sensitivity.
2
PWD measurement made on quantizer outputs in bypass mode.
3
Jitter tolerance measurements are equipment limited.
4
TDINP/N are CML inputs. If the drivers to the TDINP/N inputs are anything other than CML, they must be ac-coupled.
5
SEL0 and SEL1 have internal pull-down resistors, causing higher I
IH
.
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