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參數資料
| 型號： | ADN2819ACPZ-CML-RL1 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 運動控制電子 |
| 英文描述： | Multirate to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp |
| 中文描述： | 多速率為2.7 Gb / s的集成時鐘和數據恢復芯片限幅放大器 |
| 文件頁數： | 7/24頁 |
| 文件大小： | 570K |
| 代理商： | ADN2819ACPZ-CML-RL1 |
ADN2819
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Rev. B | Page 7 of 24
PIN 1
TOPVIEW
ADN2819
THRADJ 1
VEE 3
VREF 4
PIN 5
NIN 6
SLICEP 7
SLICEN 8
VEE 9
LOL 10
XO1 11
XO2 12
R
R
R
V
T
T
V
V
C
V
R
R
36VCC
35VCC
33VEE
32 SEL0
31 SEL1
30 SEL2
29VEE
28VCC
27VEE
26VCC
25 CF2
4
4
4
4
4
4
4
4
4
3
3
3
0
Figure 2. 48-Lead LFCSP Pin Configuration
Table 3. Pin Function Descriptions
Pin Number
1
2, 26, 28, Pad
3, 9, 16, 19, 22, 27,
29, 33, 34, 42, 43, 46
4
5
6
7
8
10
11
12
13
14
15
17
18
20, 47
21
23
24
25
30
31
32
35, 36
37
38
39
40
41
44
45
48
Mnemonic
THRADJ
VCC
VEE
Type
1
Description
AI
LOS Threshold Setting Resistor.
P
Analog Supply.
P
Ground.
VREF
PIN
NIN
SLICEP
SLICEN
LOL
XO1
XO2
REFCLKN
REFCLKP
REFSEL
TDINP
TDINN
VCC
CF1
REFSEL1
REFSEL0
CF2
SEL2
SEL1
SEL0
VCC
DATAOUTN
DATAOUTP
SQUELCH
CLKOUTN
CLKOUTP
BYPASS
SDOUT
LOOPEN
AO
AI
AI
AI
AI
DO
AO
AO
DI
DI
DI
AI
AI
P
AO
DI
DI
AO
DI
DI
DI
P
DO
DO
DI
DO
DO
DI
DO
DI
Internal VREF Voltage. Decouple to GND with 0.1 μF capacitor.
Differential Data Input.
Differential Data Input.
Differential Slice Level Adjust Input.
Differential Slice Level Adjust Input.
Loss of Lock Indicator. LVTTL active high.
Crystal Oscillator.
Crystal Oscillator.
Differential REFCLK Input. LVTTL, LVCMOS, LVPECL, LVDS (LVPECL, LVDS only at 155.52 MHz).
Differential REFCLK Input. LVTTL, LVCMOS, LVPECL, LVDS (LVPECL, LVDS only at 155.52 MHz).
Reference Source Select. 0 = on-chip oscillator with external crystal; 1 = external clock source, LVTTL.
Differential Test Data Input. CML.
Differential Test Data Input. CML.
Digital Supply.
Frequency Loop Capacitor.
Reference Frequency Select (See Table 6) LVTTL.
Reference Frequency Select (See Table 6) LVTTL.
Frequency Loop Capacitor.
Data Rate Select (See Table 5) LVTTL.
Data Rate Select (See Table 5) LVTTL.
Data Rate Select (See Table 5) LVTTL.
Output Driver Supply.
Differential Retimed Data Output. CML.
Differential Retimed Data Output. CML.
Disable Clock and Data Outputs. Active high. LVTTL.
Differential Recovered Clock Output. CML.
Differential Recovered Clock Output. CML.
Bypass CDR Mode. Active high. LVTTL.
Loss of Signal Detect Output. Active high. LVTTL.
Enable Test Data Inputs. Active high. LVTTL.
1
Type: P = Power, AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output.
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