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參數(shù)資料
| 型號： | ADP3025JRU-REEL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | High Efficiency Dual Output Power Supply Controller |
| 中文描述： | DUAL SWITCHING CONTROLLER, 350 kHz SWITCHING FREQ-MAX, PDSO38 |
| 封裝： | MO-153BD-1, TSSOP-36 |
| 文件頁數(shù)： | 12/24頁 |
| 文件大小： | 609K |
| 代理商： | ADP3025JRU-REEL |
ADP3025
CURRENT LIMITING (CLSET)
A cycle-by-cycle current limiting scheme is used by monitoring
current through the top N-channel MOSFET when it is turned
on. By measuring the voltage drop across the high-side
MOSFET,
V
DS
(
ON
)
, the use of an external sense resistor can be
omitted. The current limit value can be set by CLSET. When
CLSET is floating, the maximum
V
DS
(
ON
)
= 72 mV at room
temperature; when CLSET = 0 V, the maximum
V
DS
(
ON
)
=
300 mV at room temperature. An external resistor can be
connected between CLSET and AGND to choose a value
between 72 mV and 300 mV. The relationship between the
external resistance and the maximum
V
DS
(
ON
)
is
Rev. A | Page 12 of 24
)
kΩ
26
(
)
kΩ
110
(
mV
72
)
(
EXT
EXT
MAX
ON
DS
R
R
V
+
+
=
(1)
The temperature coefficient of R
DS(ON)
of the N-channel
MOSFET is canceled by the internal current limit circuitry, so
an accurate current limit value can be obtained over a wide
temperature range.
OUTPUT UNDERVOLTAGE PROTECTION
Each switching controller has an undervoltage protection
circuit. When the current flowing through the high-side
MOSFET reaches the current limit continuously for eight clock
cycles and the output voltage stays below 20% of the nominal
output voltage, both controllers are latched off and do not
restart until SD or SS3/SS5 is toggled, or until VIN is cycled
below 4.05 V. This feature is disabled during soft start.
OUTPUT OVERVOLTAGE AND REVERSE VOLTAGE
PROTECTION
Both converter outputs are continuously monitored for
overvoltage. If either output voltage is higher than the nominal
output voltage by more than 20%, both converters’ high-side
gate drivers (DRVH5/3) are latched off, and the low-side gate
drivers are latched on. The chip will not restart until SD or
SS5/SS3 is toggled, or until VIN is cycled below 4.05 V. The low-
side gate driver (DRVL) is kept high when the controller is in
the off-state and the output voltage is less than 93% of the
nominal output voltage. Discharging the output capacitors
through the main inductor and low-side N-channel MOSFET
causes the output to ring. This makes the output go below GND
momentarily. To prevent damage to the circuit, use a 1 A
Schottky diode in parallel with the output capacitors to clamp
the negative surge.
POWER GOOD OUTPUT (PWRGD)
The ADP3025 also provides a PWRGD signal output. During
startup, the PWRGD pin is held low until the 5 V output is
within –3% of its preset voltage. Then, after a time delay
determined by an external timing capacitor connected from
CPOR to GND, PWRGD is actively pulled up to INTVCC by an
external pull-up resistor. This delay can be calculated by
μA
1
V
2
CPOR
D
C
t
×
=
(2)
CPOR can also be used as a manual reset (MR) input. When the
5 V output is lower than the preset voltage by more than 7%,
PWRGD is immediately pulled low.
LINEAR REGULATOR CONTROLLER
The ADP3025 includes an on-board linear regulator controller.
An external NMOS can be used as the pass transistor. The
output voltage can be set by a resistor divider. The minimum
output voltage of the LDO is 800 mV, while the maximum
output voltage cannot exceed a voltage level determined by the
IC’s INTVCC voltage minus the threshold voltage of the
external
N-type MOSFET device. Assuming a INTVCC of 5 V, the
recom-mended maximum output voltage is around 2.5 V. To
ensure loop stability, a compensation network can be attached
to the COMP2/SD2 pin, as shown in Figure 17.
Large signal response limits the maximum/minimum load ratio.
When the linear regulator is loaded, the MOSFET’s gate source
voltage is at its threshold level and changes only slightly. The
loop response speed depends on the loop transfer function,
which is fast enough for most applications. However, when the
load is extremely light, the gate source voltage of the MOSFET
is much lower than its nominal value. If at this moment the load
increases suddenly, the MOSFET’s gate source capacitance
needs to be charged up, which takes time. To optimize large
signal response, not exceeding a maximum-to-minimum load
ratio of 100 to 1 is recommended.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADP3025 | High Efficiency Dual Output Power Supply Controller |
| ADP3050AR-33 | Circular Connector Cable Assembly; Connector Type A:Circular Plug; Connector Type B:Stripped End Leads; Cable Length:10ft RoHS Compliant: Yes |
| ADP3050AR-5 | Circular Connector Cable Assembly; Connector Type A:Circular Receptacle; Connector Type B:Stripped End Leads; Cable Length:10ft RoHS Compliant: Yes |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADP3025JRUZ-REEL | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| ADP3026 | 制造商:AD 制造商全稱:Analog Devices 功能描述:High-Efficiency Notebook Computer Power Supply Controller |
| ADP3026ARU | 制造商:AD 制造商全稱:Analog Devices 功能描述:High-Efficiency Notebook Computer Power Supply Controller |
| ADP3026JRUZ-REEL | 制造商:Rochester Electronics LLC 功能描述:DUAL OUTPUT SYNCHRNOUS BUCK CONTROLLER - Tape and Reel 制造商:Analog Devices 功能描述: |
| ADP3031 | 制造商:AD 制造商全稱:Analog Devices 功能描述:2 MHz PWM Boost Switching Regulator |
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