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參數(shù)資料
| 型號： | ADP3180JRU-REEL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 6-Bit Programmable 2-, 3-, 4-Phase Synchronous Buck Controller |
| 中文描述： | SWITCHING CONTROLLER, 4000 kHz SWITCHING FREQ-MAX, PDSO28 |
| 封裝： | MO-153-AE, TSSOP-28 |
| 文件頁數(shù)： | 15/20頁 |
| 文件大?。?/td> | 529K |
| 代理商： | ADP3180JRU-REEL7 |
ADP3180
–15–
being dominant, the following expression shows the total power
being dissipated in each synchronous MOSFET in terms of
the ripple current per phase (
I
R
) and average total output cur-
rent (
I
O
);
P
D
I
n
n
I
n
R
SF
O
SF
R
SF
DS SF
=
(
)
×
+
×
×
)
1
1
12
2
2
(15)
Knowing the maximum output current being designed for and
the maximum allowed power dissipation, one can find the
required R
DS(ON)
for the MOSFET. For D-PAK MOSFETs up to
an ambient temperature of 50oC, a safe limit for P
SF
is 1 W–1.5 W
at 120oC junction temperature. Thus, for our example (65 A
maximum), we find R
DS(SF)
(per MOSFET) < 8.7 m
W
. This
R
DS(SF)
is also at a junction temperature of about 120oC, so we
need to make sure we account for this when making this selec-
tion. For our example, we selected two lower side MOSFETs
at 7 m
W
each at room temperature, which gives 8.4 m
W
at high
temperature.
Another important factor for the synchronous MOSFET is the
input capacitance and feedback capacitance. The ratio of the
feedback to input needs to be small (less than 10% is recom-
mended) to prevent accidental turn-on of the synchronous
MOSFETs when the switch node goes high.
Also, the time to switch the synchronous MOSFETs off should
not exceed the non overlap dead time of the MOSFET driver
(40 ns typical for the ADP3418). The output impedance of the
driver is about 2
W
and the typical MOSFET input gate resis-
tances are about 1
W
–2
W
, so a total gate capacitance of less than
6000 pF should be adhered to. Since there are two MOSFETs in
parallel, we should limit the input capacitance for each synchro-
nous MOSFET to 3000 pF.
The high side (main) MOSFET has to be able to handle two
main power dissipation components: conduction and switching
losses. The switching loss is related to the amount of time it takes
for the main MOSFET to turn on and off and to the current and
voltage that are being switched. Basing the switching speed on
the rise and fall time of the gate driver impedance and MOSFET
input capacitance, the following expression provides an approxi-
mate value for the switching loss per main MOSFET, where
n
MF
is the total number of main MOSFETs:
P
f
V
I
n
R
n
n
C
S MF
SW
CC
O
MF
G
MF
ISS
)
=
×
×
×
×
×
×
2
(16)
Here,
R
G
is the total gate resistance (2
W
for the ADP3418 and
about 1
W
for typical high speed switching MOSFETs, making
R
G
= 3
W
) and
C
ISS
is the input capacitance of the main MOS-
FET. It is interesting to note that adding more main MOSFETs
(
n
MF
) does not really help the switching loss per MOSFET since
the additional gate capacitance slows down switching. The best
thing to reduce switching loss is to use lower gate capacitance
devices.
The conduction loss of the main MOSFET is given by the fol-
lowing, where
R
DS(MF)
is the ON resistance of the MOSFET:
P
D
I
n
n
I
n
R
C MF
O
MF
R
MF
DS MF
)
)
=
×
+
×
×
2
2
1
12
(17)
Typically, for main MOSFETs, one wants the highest speed (low
C
ISS
) device, but these usually have higher ON resistance. One
must select a device that meets the total power dissipation (about
REV. 0
1.5 W for a single D-PAK) when combining the switching and
conduction losses.
For our example, we have selected an Infineon IPD12N03L as
the main MOSFET (three total; n
MF
= 3), with a C
ISS
= 1460 pF
(max) and R
DS(MF)
= 14 m
W
(max at T
J
= 120oC) and an Infineon
IPD06N03L as the synchronous MOSFET (six total; n
SF
= 6),
with C
ISS
= 2370 pF (max) and R
DS(SF)
= 8.4 m
W
(max at T
J
=
120oC). The synchronous MOSFET C
ISS
is less than 3000 pF,
satisfying that requirement. Solving for the power dissipation per
MOSFET at I
O
= 65 A and I
R
= 8.2 A yields 863 mW for each
synchronous MOSFET and 1.44 W for each main MOSFET.
These numbers work well considering there is usually more PCB
area available for each main MOSFET versus each synchronous
MOSFET.
One last thing to look at is the power dissipation in the driver
for each phase. This is best described in terms of the Q
G
for the
MOSFETs and is given by the following, where
Q
GMF
is the total
gate charge for each main MOSFET and
Q
GSF
is the total gate
charge for each synchronous MOSFET:
P
f
n
n
Q
n
Q
I
V
DRV
SW
×
MF
GMF
SF
GSF
CC
CC
=
×
×
+
×
(
)
+
×
2
Also shown is the standby dissipation factor (
I
CC
times the
V
CC
)
for the driver. For the ADP3418, the maximum dissipation
should be less than 400 mW. For our example, with I
CC
= 7 mA,
Q
GMF
= 22.8 nC, and
Q
GSF
= 34.3 nC, we find 260 mW in each
driver, which is below the 400 mW dissipation limit. See the
ADP3418 data sheet for more details.
Ramp Resistor
Selection
The ramp resistor (
R
R
) is used for setting the size of the internal
PWM ramp. The value of this resistor is chosen to provide the
best combination of thermal balance, stability, and transient
response. The following expression is used for determining the
optimum value:
R
A
L
A
0 2
.
R
600
C
R
nH
×
m
pF
k
R
R
×
×
4 2
.
D
DS
R
R
=
×
×
×
=
3 5
=
3
5
381
(19)
where
A
R
is the internal ramp amplifier gain,
A
D
is the current
balancing amplifier gain,
R
DS
is the total low side MOSFET ON
resistance, and
C
R
is the internal ramp capacitor value. The clos-
est standard 1% resistor value is 383 k
W
.
The internal ramp voltage magnitude can be calculated using:
(
×
×
×
(
×
×
383
5
267
The size of the internal ramp can be made larger or smaller. If
it is made larger, stability and transient response will improve,
but thermal balance will degrade. Likewise, if the ramp is made
smaller, thermal balance will improve at the sacrifice of transient
response and stability. The factor of three in the denominator of
Equation 19 sets a ramp size that gives an optimal balance for
good stability, transient response, and thermal balance.
V
A
D
V
R
.
C
1 0 125
.
f
V
V
k
pF
kHz
V
R
R
VID
R
R
SW
R
=
×
)
×
=
)
×
=
1
0 2
1 5
.
0 51
.
(20)
(18)
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