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參數(shù)資料
| 型號(hào)： | ADSP-21061LKB-160 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | ADSP-2106x SHARC DSP Microcomputer Family |
| 中文描述： | 48-BIT, 40 MHz, OTHER DSP, PBGA225 |
| 封裝： | PLASTIC, BGA-225 |
| 文件頁(yè)數(shù)： | 28/47頁(yè) |
| 文件大小： | 367K |
| 代理商： | ADSP-21061LKB-160 |
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–28–
ADSP-21061/ADSP-21061L
REV. B
ADSP-21061 (5 V)
Min
ADSP-21061L (3.3 V)
Min
Parameter
Max
Max
Unit
Read Cycle
Timing Requirements:
t
SADRDL
t
HADRDH
t
WRWH
t
DRDHRDY
t
DRDHRDY
Address Setup/
CS
Low before
RD
Low
1
Address Hold/
CS
Hold Low after
RD
RD
/
WR
High Width
RD
High Delay after REDY (O/D) Disable
RD
High Delay after REDY (A/D) Disable
0
0
6
0
0
0
0
6
0
0
ns
ns
ns
ns
ns
Switching Characteristics:
t
SDATRDY
t
DRDYRDL
t
RDYPRD
t
HDARWH
Data Valid before REDY Disable from Low
REDY (O/D) or (A/D) Low Delay after
RD
Low
REDY (O/D) or (A/D) Low Pulsewidth for Read
Data Disable after
RD
High
2
2
ns
ns
ns
ns
10
13.5
45 + DT
2
45 + DT
2
8
8
Write Cycle
Timing Requirements:
t
SCSWRL
t
HCSWRH
t
SADWRH
t
HADWRH
t
WWRL
t
WRWH
t
DWRHRDY
t
SDATWH
t
SDATWH
(50 MHz) Data Setup before
WR
High, t
CK
= 20 ns
2
t
HDATWH
Data Hold after
WR
High
CS
Low Setup before
WR
Low
CS
Low Hold after
WR
High
Address Setup before
WR
High
Address Hold after
WR
High
WR
Low Width
RD
/
WR
High Width
WR
High Delay after REDY (O/D) or (A/D) Disable
Data Setup before
WR
High
0
0
5
2
8
6
0
3
2.5
1
0
0
5
2
8
6
0
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
Switching Characteristics:
t
DRDYWRL
t
RDYPWR
t
SRDYCK
REDY (O/D) or (A/D) Low Delay after
WR
/
CS
Low
REDY (O/D) or (A/D) Low Pulsewidth for Write
REDY (O/D) or (A/D) Disable to CLKIN
11
13.5
ns
ns
ns
15
1 + 7DT/16
15
1 + 7DT/16
8 + 7DT/16
8 + 7DT/16
NOTES
1
Not required if
RD
and address are valid t
HBGRCSV
after
HBG
goes low. For first access after
HBR
asserted, ADDR
31-0
must be a non-MMS value 1/2 t
CLK
before
RD
or
WR
goes low or by t
HBGRCSV
after
HBG
goes low. This is easily accomplished by driving an upper address signal high when
HBG
is asserted. See the Host Proces-
sor Control of the ADSP-2106x section in the
ADSP-2106x SHARC User’s Manual, Second Edition
.
2
This specification applies to the ADSP-21061KS-200 (5 V, 50 MHz) operating at t
CK
< 25 ns. For all other devices, use the preceding timing specification of the
same name.
Asynchronous Read/Write—Host to ADSP-21061
Use these specifications for asynchronous host processor accesses
of an ADSP-21061, after the host has asserted
CS
and
HBR
(low). After
HBG
is returned by the ADSP-21061, the host can
drive the
RD
and
WR
pins to access the ADSP-21061’s internal
memory or IOP registers.
HBR
and
HBG
are assumed low for
this timing.
CLKIN
REDY (O/D)
O/D = OPEN DRAIN, A/D = ACTIVE DRIVE
t
SRDYCK
REDY (A/D)
Figure 18a. Synchronous REDY Timing
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADSP-21061LKB-176 | ADSP-2106x SHARC DSP Microcomputer Family |
| ADSP-21061LKS-160 | ADSP-2106x SHARC DSP Microcomputer Family |
| ADSP-21061LKS-176 | ADSP-2106x SHARC DSP Microcomputer Family |
| ADSP-21062CS-160 | ADSP-2106x SHARC DSP Microcomputer Family |
| ADSP-21062KS-133 | ADSP-2106x SHARC DSP Microcomputer Family |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADSP-21061LKB-176 | 制造商:AD 制造商全稱:Analog Devices 功能描述:DSP Microcomputer Family |
| ADSP-21061LKBZ-160 | 功能描述:IC DSP CONTROLLER 32BIT 225-BGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:SHARC® 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤(pán) |
| ADSP21061LKS160 | 制造商:Analog Devices 功能描述:DSP Floating-Point 32-Bit 40MHz 40MIPS 240-Pin MQFP Tray |
| ADSP-21061LKS-160 | 制造商:Rochester Electronics LLC 功能描述:ADSP-21061 1MBIT,40MHZ, 3V SHARC - Bulk 制造商:Analog Devices 功能描述:IC SHARC DSP 40MHZ 21061 MQFP240 |
| ADSP-21061LKS-176 | 制造商:Analog Devices 功能描述:DSP Floating-Point 32-Bit 44MHz 44MIPS 240-Pin MQFP Tray 制造商:Rochester Electronics LLC 功能描述:ADSP-21061L 44HZ, 3V SHARC - Bulk |
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