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參數(shù)資料
| 型號： | ADSP-21061LKB-160 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | ADSP-2106x SHARC DSP Microcomputer Family |
| 中文描述： | 48-BIT, 40 MHz, OTHER DSP, PBGA225 |
| 封裝： | PLASTIC, BGA-225 |
| 文件頁數(shù)： | 39/47頁 |
| 文件大小： | 367K |
| 代理商： | ADSP-21061LKB-160 |
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ADSP-21061/ADSP-21061L
–39–
REV. B
Example System Hold Time Calculation
To determine the data output hold time in a particular system,
first calculate t
DECAY
using the equation given above. Choose
V
to be the difference between the ADSP-2106x’s output voltage
and the input threshold for the device requiring the hold time. A
typical
V will be 0.4 V. C
L
is the total bus capacitance (per
data line), and I
L
is the total leakage or three-state current (per
data line). The hold time will be t
DECAY
plus the minimum
disable time (i.e., t
DATRWH
for the write cycle).
REFERENCE
SIGNAL
t
DIS
OUTPUT STARTS
DRIVING
V
OH (MEASURED)
–
V
V
OL (MEASURED)
+ V
t
DECAY
t
MEASURED
V
OH (MEASURED)
V
OL (MEASURED)
2.0V
1.0V
V
OH (MEASURED)
V
OL (MEASURED)
HIGH-IMPEDANCE STATE.
TEST CONDITIONS CAUSE
THIS VOLTAGE TO BE
APPROXIMATELY 1.5V
OUTPUT STOPS
DRIVING
t
ENA
OUTPUT
Figure 24. Output Enable/Disable
+1.5V
50pF
TO
OUTPUT
PIN
I
OL
I
OH
Figure 25. Equivalent Device Loading for AC Measure-
ments (Includes All Fixtures)
Capacitive Loading
Output delays and holds are based on standard capacitive loads:
50 pF on all pins (see Figure 25). The delay and hold specifica-
tions given should be derated by a factor of 1.5 ns/50 pF for
loads other than the nominal value of 50 pF. Figures 28–29,
32–33 show how output rise time varies with capacitance. Fig-
ures 30, 34 show graphically how output delays and holds vary
with load capacitance. (Note that this graph or derating does
not apply to output disable delays; see the previous section
Output Disable Time
under Test Conditions.) The graphs of
Figures 28, 29 and 30 may not be linear outside the ranges
shown.
INPUT OR
OUTPUT
1.5V
1.5V
Figure 26. Voltage Reference Levels for AC Measure-
ments (Except Output Enable/Disable)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADSP-21061LKB-176 | ADSP-2106x SHARC DSP Microcomputer Family |
| ADSP-21061LKS-160 | ADSP-2106x SHARC DSP Microcomputer Family |
| ADSP-21061LKS-176 | ADSP-2106x SHARC DSP Microcomputer Family |
| ADSP-21062CS-160 | ADSP-2106x SHARC DSP Microcomputer Family |
| ADSP-21062KS-133 | ADSP-2106x SHARC DSP Microcomputer Family |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADSP-21061LKB-176 | 制造商:AD 制造商全稱:Analog Devices 功能描述:DSP Microcomputer Family |
| ADSP-21061LKBZ-160 | 功能描述:IC DSP CONTROLLER 32BIT 225-BGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:SHARC® 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP21061LKS160 | 制造商:Analog Devices 功能描述:DSP Floating-Point 32-Bit 40MHz 40MIPS 240-Pin MQFP Tray |
| ADSP-21061LKS-160 | 制造商:Rochester Electronics LLC 功能描述:ADSP-21061 1MBIT,40MHZ, 3V SHARC - Bulk 制造商:Analog Devices 功能描述:IC SHARC DSP 40MHZ 21061 MQFP240 |
| ADSP-21061LKS-176 | 制造商:Analog Devices 功能描述:DSP Floating-Point 32-Bit 44MHz 44MIPS 240-Pin MQFP Tray 制造商:Rochester Electronics LLC 功能描述:ADSP-21061L 44HZ, 3V SHARC - Bulk |
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