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| 型號(hào)： | ADSP-21160N |
| 廠商： | Analog Devices, Inc. |
| 元件分類(lèi)： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | Cap-Free, NMOS, 150mA Low Dropout Regulator with Reverse Current Protection |
| 中文描述： | 無(wú)電容，NMOS管，150mA的低壓差穩(wěn)壓器的反向電流保護(hù) |
| 文件頁(yè)數(shù)： | 2/53頁(yè) |
| 文件大小： | 1680K |
| 代理商： | ADSP-21160N |
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This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
2
REV. PrB
For current information contact Analog Devices at 800/262-5643
ADSP-21160N
April 2002
PRELIMINARY TECHNICAL DATA
FEATURES (CONTINUED)
Single Instruction Multiple Data (SIMD)
Architecture Provides:
Two Computational Processing Elements
Concurrent Execution—Each Processing Element
Executes the Same Instruction, but Operates on
Different Data
Code Compatibility—at Assembly Level, Uses the
Same Instruction Set as the ADSP-2106x
SHARC DSPs
Parallelism in Buses and Computational Units Allows:
Single-cycle Execution (with or without SIMD) of: A
Multiply Operation, An ALU Operation, A Dual
Memory Read or Write, and An Instruction Fetch
Transfers Between Memory and Core at up to Four
32-Bit Floating- or Fixed-Point Words per Cycle
Accelerated FFT Butterfly Computation Through a
Multiply with Add and Subtract
4M Bits On-Chip Dual-Ported SRAM for Independent
Access by Core Processor, Host, and DMA
DMA Controller supports:
14 Zero-Overhead DMA Channels for Transfers Between
ADSP-21160N Internal Memory and External Memory,
External Peripherals, Host Processor, Serial Ports, or
Link Ports
64-Bit Background DMA Transfers at Core Clock Speed,
in Parallel with Full-Speed Processor Execution
665M Bytes/s Transfer Rate Over IOP Bus
Host Processor Interface to 16- and 32-Bit
Microprocessors
4G Word Address Range for Off-Chip Memory
Memory Interface Supports Programmable Wait State
Generation and Page-Mode for Off-Chip Memory
Multiprocessing Support Provides:
Glueless Connection for Scalable DSP Multiprocessing
Architecture
Distributed On-Chip Bus Arbitration for Parallel Bus
Connect of up to Six ADSP-21160Ns plus Host
Six Link Ports for Point-To-Point Connectivity and Array
Multiprocessing
Serial Ports Provide:
Two 47.5M Bits/s Synchronous Serial Ports with
Companding Hardware
Independent Transmit and Receive Functions
TDM Support for T1 and E1 Interfaces
64-Bit Wide Synchronous External Port Provides:
Glueless Connection to Asynchronous and SBSRAM
External Memories
Up to 47.5 MHz Operation
GENERAL DESCRIPTION
The ADSP-21160N SHARC DSP is the second iteration
of the ADSP-21160. Built in a 0.18 micron CMOS process,
it offers higher performance and lower power consumption
than its predecessor, the ADSP-21160M. Easing portabil-
ity, the ADSP-21160N is application source code
compatible with first generation ADSP-2106x SHARC
DSPs in SISD (Single Instruction, Single Data) mode. To
take advantage of the processor’s SIMD (Single Instruction,
Multiple Data) capability, some code changes are needed.
Like other SHARCs, the ADSP-21160N is a 32-bit
processor that is optimized for high performance DSP appli-
cations. The ADSP-21160N includes an 95 MHz core, a
dual-ported on-chip SRAM, an integrated I/O processor
with multiprocessing support, and multiple internal buses
to eliminate I/O bottlenecks.
The ADSP-21160N introduces Single-Instruction,
Multiple-Data (SIMD) processing. Using two computa-
tional units (ADSP-2106x SHARC DSPs have one), the
ADSP-21160N can double performance versus the
ADSP-2106x on a range of DSP algorithms.
Fabricated in a state of the art, high speed, low power
CMOS process, the ADSP-21160N has a 10.5 ns instruc-
tion cycle time. With its SIMD computational hardware
running at 95 MHz, the ADSP-21160N can perform 570
million math operations per second.
Table 1
shows performance benchmarks for the
ADSP-21160N.
These benchmarks provide single-channel extrapolations of
measured dual-channel processing performance. For more
information on benchmarking and optimizing DSP code for
single- and dual-channel processing, see Analog Devices’s
website.
The ADSP-21160N continues SHARC’s industry-leading
standards of integration for DSPs, combining a
high-performance 32-bit DSP core with integrated, on-chip
system features. These features include a 4M-bit dual
ported SRAM memory, host processor interface, I/O
Table 1. ADSP-21160N Benchmarks
Benchmark Algorithm
Speed
1024 Point Complex FFT (Radix 4, with
reversal)
FIR Filter (per tap)
IIR Filter (per biquad)
Matrix Multiply (pipelined)
[3 3] [3 1]
Matrix Multiply (pipelined)
[4 4] [4 1]
Divide (y/x)
Inverse Square Root
DMA Transfer Rate
96 μs
5.25 ns
21 ns
47.25 ns
84 ns
31.5 ns
47.25 ns
665M Bytes/s
相關(guān)PDF資料 |
PDF描述 |
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| ADSP-21160NCB-TBD | Cap-Free, NMOS, 150mA Low Dropout Regulator with Reverse Current Protection |
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| ADSP-21161NCCA-100 | DSP Microcomputer |
| ADSP-21161NKCA-100 | DSP Microcomputer |
| ADSP-21262SBBC-150 | Embedded Processor |
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| ADSP-21160NCB-100 | 功能描述:IC DSP CONTROLLER 32BIT 400BGA RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:SHARC® 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類(lèi)型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類(lèi)型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤(pán) |
| ADSP-21160NCB-TBD | 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:DSP Microcomputer |
| ADSP-21160NCBZ-100 | 功能描述:IC DSP CONTROLLER 32BIT 400-PBGA RoHS:是 類(lèi)別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:SHARC® 標(biāo)準(zhǔn)包裝:40 系列:TMS320DM64x, DaVinci™ 類(lèi)型:定點(diǎn) 接口:I²C，McASP，McBSP 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類(lèi)型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:548-FCBGA（27x27） 包裝:托盤(pán) 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| ADSP-21160NCE-100 | 制造商:Analog Devices 功能描述: |
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