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| 型號： | ADSP-21160N |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | Cap-Free, NMOS, 150mA Low Dropout Regulator with Reverse Current Protection |
| 中文描述： | 無電容，NMOS管，150mA的低壓差穩(wěn)壓器的反向電流保護(hù) |
| 文件頁數(shù)： | 37/53頁 |
| 文件大小： | 1680K |
| 代理商： | ADSP-21160N |
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PRELIMINARY TECHNICAL DATA
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
37
REV. PrB
For current information contact Analog Devices at 800/262-5643
ADSP-21160N
April 2002
DMA Handshake
These specifications describe the three DMA handshake modes. In all three modes
DMAR
is used to initiate transfers. For
handshake mode,
DMAG
controls the latching or enabling of data externally. For external handshake mode, the data transfer
is controlled by the ADDR31–0,
RDx
,
WRx
, PAGE,
MS3–0
, ACK, and
DMAG
signals. For Paced Master mode, the data
transfer is controlled by ADDR31–0,
RDx
,
WRx
,
MS3–0
, and ACK (not
DMAG
). For Paced Master mode, the Memory
Read-Bus Master, Memory Write-Bus Master, and Synchronous Read/Write-Bus Master timing specifications for
ADDR31–0,
RDx
,
WRx
,
MS3–0
, PAGE, DATA63–0, and ACK also apply.
Table 18. DMA Handshake
Parameter
Timing Requirements:
t
SDRC
t
WDR
t
SDATDGL
t
HDATIDG
t
DATDRH
t
DMARLL
t
DMARH
Switching Characteristics:
t
DDGL
t
WDGH
t
WDGL
t
HDGC
t
VDATDGH
t
DATRDGH
t
DGWRL
t
DGWRH
t
DGWRR
t
DGRDL
t
DRDGH
t
DGRDR
t
DGWR
Min
Max
Unit
DMARx
Setup Before CLKIN
1
DMARx
Width Low (Nonsynchronous)
2
Data Setup After
DMAGx
Low
3
Data Hold After
DMAGx
High
Data Valid After
DMARx
High
3
DMARx
Low Edge to Low Edge
4
DMARx
Width High
2
1
Only required for recognition in the current cycle.
2
Maximum throughput using
DMARx/DMAGx
handshaking equals t
WDR
+ t
DMARH
= (0.5t
CCLK
+1) + (0.5t
CCLK
+1)=12.5 ns (80 MHz). This throughput
limit applies to non-synchronous access mode only.
3
t
SDATDGL
is the data setup requirement if
DMARx
is not being used to hold off completion of a write. Otherwise, if
DMARx
low holds off completion of
the write, the data can be driven t
DATDRH
after
DMARx
is brought high.
4
Use t
DMARLL
if
DMARx
transitions synchronous with CLKIN. Otherwise, use t
WDR
and t
DMARH
.
5
t
VDATDGH
is valid if
DMARx
is not being used to hold off completion of a read. If
DMARx
is used to prolong the read, then
t
VDATDGH
= t
CK
– .25t
CCLK
– 8 + (n × t
CK
) where n equals the number of extra cycles that the access is prolonged.
6
See
Example System Hold Time Calculation on page 47
for calculation of hold times given capacitive and dc loads.
7
This parameter applies for synchronous access mode only.
3
0.5t
CCLK
+1
ns
ns
ns
ns
ns
ns
ns
t
CK
–0.5t
CCLK
–7
2
t
CK
+3
t
CK
0.5t
CCLK
+1
DMAGx
Low Delay After CLKIN
DMAGx
High Width
DMAGx
Low Width
DMAGx
High Delay After CLKIN
Data Valid Before
DMAGx
High
5
Data Disable After
DMAGx
High
6
WRx
Low Before
DMAGx
Low
DMAG
x Low Before
WRx
High
WRx
High Before
DMAGx
High
7
RDx
Low Before
DMAGx
Low
RDx
Low Before
DMAGx
High
RDx
High Before
DMAGx
High
7
DMAGx
High to
WRx
,
RDx
,
DMAGx
Low
Address/Select Valid to
DMAGx
High
Address/Select Hold after
DMAGx
High
W = (number of wait states specified in WAIT register) t
CK
.
HI = t
CK
(if data bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
0.25t
CCLK
+1
0.5t
CCLK
–1+HI
t
CK
–0.5t
CCLK
–1
t
CK
–0.25t
CCLK
+1.5
t
CK
–0.25t
CCLK
–8
0.25t
CCLK
–3
–1.5
t
CK
–0.5t
CCLK
–2+W
–1.5
–1.5
t
CK
–0.5t
CCLK
–2+W
–1.5
0.5t
CCLK
–2+HI
0.25t
CCLK
+9
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
CK
–0.25t
CCLK
+9
t
CK
–0.25t
CCLK
+5
0.25t
CCLK
+1.5
2
2
2
2
t
DADGH
t
DDGHA
18
1
ns
ns
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