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| 型號： | ADSP-21160N |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | Cap-Free, NMOS, 150mA Low Dropout Regulator with Reverse Current Protection |
| 中文描述： | 無電容，NMOS管，150mA的低壓差穩(wěn)壓器的反向電流保護 |
| 文件頁數(shù)： | 3/53頁 |
| 文件大?。?/td> | 1680K |
| 代理商： | ADSP-21160N |
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This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
3
REV. PrB
For current information contact Analog Devices at 800/262-5643
ADSP-21160N
April 2002
PRELIMINARY TECHNICAL DATA
processor that supports 14 DMA channels, two serial ports,
six link ports, external parallel bus, and glueless
multiprocessing.
The functional block diagram
on page 1
shows a block
diagram of the ADSP-21160N, illustrating the following
architectural features:
Two processing elements, each made up of an ALU, Mul-
tiplier, Shifter, and Data Register File
Data Address Generators (DAG1, DAG2)
Program sequencer with instruction cache
PM and DM buses capable of supporting four 32-bit data
transfers between memory and the core every core
processor cycle
Interval timer
On-Chip SRAM (4M bits)
External port that supports:
Interfacing to off-chip memory peripherals
Glueless multiprocessing support for six
ADSP-21160N SHARCs
Host port
DMA controller
Serial ports and link ports
JTAG test access port
Figure 1
shows a typical single-processor system. A multi-
processing system appears in
Figure 4
.
ADSP-21160N Family Core Architecture
The ADSP-21160N includes the following archi-
tectural features of the ADSP-2116x family core. The
ADSP-21160N is code compatible at the assembly level
with the ADSP-2106x and ADSP-21161.
SIMD Computational Engine
The ADSP-21160N contains two computational process-
ing elements that operate as a Single Instruction Multiple
Data (SIMD) engine. The processing elements are referred
to as PEX and PEY, and each contains an ALU, multiplier,
shifter, and register file. PEX is always active, and PEY may
be enabled by setting the PEYEN mode bit in the MODE1
register. When this mode is enabled, the same instruction
is executed in both processing elements, but each processing
element operates on different data. This architecture is
efficient at executing math-intensive DSP algorithms.
Entering SIMD mode also has an effect on the way data is
transferred between memory and the processing elements.
When in SIMD mode, twice the data bandwidth is required
to sustain computational operation in the processing
elements. Because of this requirement, entering SIMD
mode also doubles the bandwidth between memory and the
processing elements. When using the DAGs to transfer data
in SIMD mode, two data values are transferred with each
access of memory or the register file.
Independent, Parallel Computation Units
Within each processing element is a set of computational
units. The computational units consist of an arith-
metic/logic unit (ALU), multiplier, and shifter. These units
perform single-cycle instructions. The three units within
each processing element are arranged in parallel, maximiz-
ing computational throughput. Single multifunction
instructions execute parallel ALU and multiplier opera-
tions. In SIMD mode, the parallel ALU and multiplier
operations occur in both processing elements. These com-
putation units support IEEE 32-bit single-precision
floating-point, 40-bit extended precision floating-point,
and 32-bit fixed-point data formats.
Data Register File
A general-purpose data register file is contained in each
processing element. The register files transfer data between
the computation units and the data buses, and store inter-
mediate results. These 10-port, 32-register (16 primary, 16
secondary) register files, combined with the ADSP-2116x
enhanced Harvard architecture, allow unconstrained data
flow between computation units and internal memory. The
registers in PEX are referred to as R0–R15 and in PEY
as S0–S15.
Single-Cycle Fetch of Instruction and Four Operands
The ADSP-21160N features an enhanced Harvard archi-
tecture in which the data memory (DM) bus transfers data,
and the program memory (PM) bus transfers both instruc-
tions and data (see the functional block diagram
on page 1
).
Figure 1. Single-Processor System
3
4
RESET
JTAG
6
ADSP-21160
CLKIN
BMS
CLOCK
LINK
DEVICES
(6 MAX)
(OPTIONAL)
CS
BOOT
EPROM
(OPTIONAL)
ADDR
MEMORY/
MAPPED
DEVICES
(OPTIONAL)
OE
WE
DATA
DMA DEVICE
(OPTIONAL)
DATA
ADDR
DATA
HOST
PROCESSOR
INTERFACE
(OPTIONAL)
CS
RDx
WRx
PAGE
CLKOUT
DMAR1–2
DMAG1–2
ACK
MS3–0
BR1–6
IRQ2–0
FLAG3–0
TIMEXP
LXCLK
LXACK
LXDAT7–0
TCLK0
RCLK0
RPBA
ID2–0
4
CLK_CFG3–0
EBOOT
LBOOT
DR0
DT0
TFS0
TCLK1
RCLK1
DR1
DT1
RSF1
TFS1
SERIAL
DEVICE
(OPTIONAL)
SERIAL
DEVICE
(OPTIONAL)
PA
REDY
HBG
HBR
SBTS
DATA63–0
DATA
ADDR
CS
ACK
ADDR31–0
D
C
A
CIF
BRST
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