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參數資料
| 型號： | ADSP-21266 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | SHARC Embedded Processor |
| 中文描述： | SHARC處理器嵌入式處理器 |
| 文件頁數： | 11/44頁 |
| 文件大小： | 426K |
| 代理商： | ADSP-21266 |
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ADSP-21266
Rev. B
|
Page 11 of 44
|
May 2005
PIN FUNCTION DESCRIPTIONS
ADSP-21266 pin definitions are listed below. Inputs identified
as synchronous (S) must meet timing requirements with respect
to CLKIN (or with respect to TCK for TMS, TDI). Inputs iden-
tified as asynchronous (A) can be asserted asynchronously to
CLKIN (or to TCK for TRST). Tie or pull unused inputs to
V
DDEXT
or GND, except for the following:
DAI_Px, SPICLK, MISO, MOSI, EMU, TMS,TRST, TDI
and AD15
–
0 (NOTE: These pins have internal pull-up
resistors.)
The following symbols appear in the Type column of
Table 3
:
A = asynchronous, G = ground, I = input, O = output,
P = power supply, S = synchronous, (A/D) = active drive,
(O/D) = open drain, and T = three-state.
Table 3. Pin Descriptions
Pin
AD15
–
0
Type
I/O/T
State During and
After Reset
Rev. 0.1 silicon—
AD15
–
0 pins are
driven low both
during and after
reset.
Rev. 0.2 silicon—
AD15
–
0 pins are
three-stated and
pulled high both
during and after
reset.
Function
Parallel Port Address/Data.
The ADSP-21266 parallel port and its corresponding
DMA unit output addresses and data for peripherals on these multiplexed pins. The
multiplex state is determined by the ALE pin. The parallel port can operate in either
8-bit or 16-bit mode. Each AD pin has a 22.5 k
internal pull-up resistor. See
Address
Data Modes on Page 14
for details of the AD pin operation.
For 8-bit mode: ALE is automatically asserted whenever a change occurs in the
upper 16 external address bits, A23
–
8; ALE is used in conjunction with an external
latch to retain the values of the A23
–
8.
For 16-bit mode: ALE is automatically asserted whenever a change occurs in the
address bits, A15
–
0; ALE is used in conjunction with an external latch to retain the
values of the A15
–
0. To use these pins as flags (FLAG15
–
0) set (=1) Bit 20 of the
SYSCTL register and disable the parallel port. See
Table 4 on Page 14
for a list of how
the AD15
–
0 pins map to the flag pins. When configured in the IDP_PDAP_CTL
register, the IDP Channel 0 can use these pins for parallel input data.
Parallel Port Read Enable.
RD is asserted low whenever the DSP reads 8-bit or
16-bit data from an external memory device. When AD15
–
0 are flags, this pin
remains deasserted.
Parallel Port Write Enable.
WR is asserted low whenever the DSP writes 8-bit or
16-bit data to an external memory device. When AD15
–
0 are flags, this pin remains
deasserted.
Parallel Port Address Latch Enable.
ALE is asserted whenever the DSP drives a
new address on the parallel port address pin. On reset, ALE is active high. However,
it can be reconfigured using software to be active low. When AD15
–
0 are flags, this
pin remains deasserted.
Flag Pins.
Each FLAG pin is configured via control bits as either an input or output.
As an input, it can be tested as a condition. As an output, it can be used to signal
external peripherals. These pins can be used as an SPI interface slave select output
during SPI mastering. These pins are also multiplexed with the IRQx and the TIMEXP
signals.
In SPI master boot mode, FLAG0 is the slave select pin that must be connected to
an SPI EPROM. FLAG0 is configured as a slave select during SPI master boot. When
Bit 16 is set (=1) in the SYSCTL register, FLAG0 is configured as IRQ0.
When Bit 17 is set (=1) in the SYSCTL register, FLAG1 is configured as IRQ1.
When Bit 18 is set (=1) in the SYSCTL register, FLAG2 is configured as IRQ2.
When Bit 19 is set (=1) in the SYSCTL register, FLAG3 is configured as TIMEXP, which
indicates that the system timer has expired.
RD
O
Output only, driven
high
1
WR
O
Output only, driven
high
1
ALE
O
Output only, driven
low
1
FLAG3
–
0
I/O/A
Three-state
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