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參數資料
| 型號： | ADSP-21266 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | SHARC Embedded Processor |
| 中文描述： | SHARC處理器嵌入式處理器 |
| 文件頁數： | 29/44頁 |
| 文件大小： | 426K |
| 代理商： | ADSP-21266 |
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ADSP-21266
Rev. B
|
Page 29 of 44
|
May 2005
Serial Ports
To determine whether communication is possible between two
devices at clock speed n, the specifications in
Table 24
,
Table 25
,
Table 26
,
Table 27
,
Figure 21
, and
Figure 22
must be confirmed:
1) frame sync delay and frame sync setup and hold; 2) data delay
and data setup and hold; and 3) SCLK width.
Serial port signals (SCLK, FS, DxA,/DxB) are routed to the
DAI_P20
–
1 pins using the SRU. Therefore, the timing specifi-
cations provided below are valid at the DAI_P20
–
1 pins.
Table 24. Serial Ports—External Clock
Parameter
Timing Requirements
t
SFSE
Min
Max
Unit
FS Setup Before SCLK
(Externally Generated FS in Either Transmit or Receive Mode)
1
FS Hold After SCLK
(Externally Generated FS in Either Transmit or Receive Mode)
1
Receive Data Setup Before Receive SCLK
1
Receive Data Hold After SCLK
1
SCLK Width
SCLK Period
2.5
ns
t
HFSE
2.5
2.5
2.5
7
20
ns
ns
ns
ns
ns
t
SDRE
t
HDRE
t
SCLKW
t
SCLK
Switching Characteristics
t
DFSE
FS Delay After SCLK
(Internally Generated FS in Either Transmit or Receive Mode)
2
FS Hold After SCLK
(Internally Generated FS in Either Transmit or Receive Mode)
2
Transmit Data Delay After Transmit SCLK
2
Transmit Data Hold After Transmit SCLK
2
7
ns
t
HOFSE
2
ns
ns
ns
t
DDTE
t
HDTE
7
2
1
Referenced to sample edge.
2
Referenced to drive edge.
Table 25. Serial Ports—Internal Clock
Parameter
Timing Requirements
t
SFSI
Min
Max
Unit
FS Setup Before SCLK
(Externally Generated FS in Either Transmit or Receive Mode)
1
FS Hold After SCLK
(Externally Generated FS in Either Transmit or Receive Mode)
1
Receive Data Setup Before SCLK
1
Receive Data Hold After SCLK
1
6
ns
t
HFSI
1.5
6
1.5
ns
ns
ns
t
SDRI
t
HDRI
Switching Characteristics
t
DFSI
t
HOFSI
t
DFSI
t
HOFSI
t
DDTI
t
HDTI
t
SCLKIW
FS Delay After SCLK (Internally Generated FS in Transmit Mode)
2
FS Hold After SCLK (Internally Generated FS in Transmit Mode)
2
FS Delay After SCLK (Internally Generated FS in Receive Mode)
2
FS Hold After SCLK (Internally Generated FS in Receive Mode)
2
Transmit Data Delay After SCLK
2
Transmit Data Hold After SCLK
2
Transmit or Receive SCLK Width
3
ns
ns
ns
ns
ns
ns
ns
–1.0
3
–1.0
3
–1.0
0.5t
SCLK
– 2
0.5t
SCLK
+ 2
1
Referenced to the sample edge.
2
Referenced to drive edge.
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